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Part: K7N403609A
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 4 Mb
-> NtRAM(FT & PP)
Description: Description = K7N403609A 128Kx36-Bit Pipelined NtRAM™ ;; Organization = 128Kx36 ;; Operating Mode = SPB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 2.4,2.6,2.8,3.0 ;; Speed-tcyc (MHz) = 250,225,200,183 ;; I/o Voltage(V) = 3.3,2.5 ;; Package = 100TQFP ;; Production Status = Eol ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7N403609A datasheet File size : 282 kB
Request For quote: Find where to buy K7N403609A
Datasheet text preview:
K7N403609A K7N401809A
Document Title
128Kx36 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 256Kx18-Bit Pipelined NtRAM TM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed DC condition at Icc and ISB. Icc ; from 440mA to 490mA at -25, from 410mA to 460mA at -22, from 390mA to 440mA at -20, from 370mA to 420mA at -18, ISB ; from 170mA from 160mA from 150mA from 140mA 1.0 to to to to 180mA 170mA 160mA 150mA at at at at -25, -22, -20, -18, Final Draft Date Jan. 20. 2000 April. 03. 2000 Remark Preliminary Preliminary
May. 15. 2000 1. Final spec release 2. Changed input & output capacitance. CIN ; from 6pF to 5pF, COUT ; from 8pF to 7pF, 3.Changed part number from K7N4036(18)01A -under 167MHz to K7N4036(18)09A -over183MHz
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
May 2000 Rev 1.0
K7N403609A K7N401809A
128Kx36 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
FEATURES
· VDD=3.3V+0.165V/-0.165V Power Supply. · VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. · Byte Writable Function. · Enable clock and suspend operation. · Single READ/WRITE control pin. · Self-Timed Write Cycle. · Three Chip Enable for simple depth expansion with no datacontention. · interleaved burst or a linear burst mode. · Asynchronous output enable control. · Power Down mode. · TTL-Level Three-State Outputs. · 100-TQFP-1420A Package.
GENERAL DESCRIPTION
The K7N403609A and K7N401809A are 4,718,592 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. The K7N403609A and K7N401809A are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol -25 -22 -20 -18 U n i t tCYC tCD tOE 4 . 0 4.4 5.0 5.4 2 . 4 2.6 2.8 3.0 2 . 4 2.6 2.8 3.0 ns ns ns
LOGIC BLOCK DIAGRAM
LBO A [0:16]or A [0:17] ADDRESS REGISTER A2~A16 or A2~A17 A0~A1
BURST ADDRESS COUNTER
A0~A1 128Kx36 , 256Kx18 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd 36 or 18
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
-2-
May 2000 Rev 1.0
K7N403609A K7N401809A
PIN CONFIGURATION(TOP VIEW)
BWd BWb
128Kx36 & 256Kx18 Pipelined NtRAMTM
BWa
BWc
CKE
ADV
N.C.
N.C. 83
CL K
CS1
CS2
CS2
VDD
VSS
WE
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
PIN NAME
SYMBOL A0 - A16 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL VDD VSS N.C. D Q a 0~ a 7 D Q b 0~ b 7 D Q c 0~c7 D Q d 0~ d 7 DQPa~P d VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43,83,84 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
LBO
VSS
Output Power Supply (2.5V or 3.3V) Output Ground
Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-3-
A16
50
DQPc DQc0 DQc1 VDDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ V SSQ DQd2 DQd3 DQd4 DQd5 V SSQ VDDQ DQd6 DQd7 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7N403609A(128Kx36)
DQPb DQb7 DQb6 V DDQ V SSQ DQb5 DQb4 DQb3 DQb2 V SSQ V DDQ DQb1 DQb0 V SS VDD VDD ZZ DQa7 DQa6 V DDQ V SSQ DQa5 DQa4 DQa3 DQa2 V SSQ V DDQ DQa1 DQa0 DQPa
May 2000 Rev 1.0
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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