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Part: K7N403609B-QC20
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 4 Mb
-> NtRAM(FT & PP)
Description: Description = K7N403609B 128Kx36-Bit Pipelined NtRAM™ ;; Organization = 128Kx36 ;; Operating Mode = SPB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 2.4,2.6,2.8,3.0 ;; Speed-tcyc (MHz) = 250,225,200 ;; I/o Voltage(V) = 3.3,2.5 ;; Package = 100TQFP ;; Production Status = Mass Production ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7N403609B-QC20 datasheet File size : 282 kB
Request For quote: Find where to buy K7N403609B-QC20
Datasheet text preview:
K7N403609B K7N403209B K7N401809B
Document Title
128Kx36/x32 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 128Kx32 & 256Kx18-Bit Pipelined NtRAMTM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed DC parameters Icc ; from 470mA to 400mA at -25, from 440mA to 360mA at -22, from 400mA to 330mA at -20, from 370mA to 310mA at -18, ISB ; from 180mA from 170mA from 160mA from 150mA ISB1 ; from 100mA 0.2 1.0 to to to to to 160mA at -25, 155mA at -22, 150mA at -20, 140mA at -18, 80mA Aug. 11. 2001 Nov. 15. 2001 Preliminary Final Draft Date May. 15. 2001 June. 12. 2001 Remark Preliminary Preliminary
1. Add x32 org. and industrial temperature 1. Final spec release 2. Changed Pin Capacitance - Cin ; from 5pF to 4pF - Cout ; from 7pF to 6pF
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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November 2001 Rev 1.0
K7N403609B K7N403209B K7N401809B
128Kx36/x32 & 256Kx18 Pipelined NtRAMTM
4Mb NtRAM(Flow Through / Pipelined) Ordering Information
Org. Part Number Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) 6.5/7.5/8.0 ns 167/133 MHz 250/225/200 MHz 6.5/7.5/8.0 ns 167/133 MHz 250/225/200 MHz 6.5/7.5/8.0 ns 167/133 MHz 250/225/200 MHz Q :100TQFP C (Commercial Temperature Range) I: (Industrial Temperature Range) PKG Temp
K7M401825B-QC(I)65/75/80 256Kx18 K 7 N 4 0 1 8 0 1 B - Q C ( I ) 1 6 / 1 3 K7N401809B-QC(I)25/22/20 K7M403225B-QC(I)65/75/80 128Kx32 K 7 N 4 0 3 2 0 1 B - Q C ( I ) 1 6 / 1 3 K7N403209B-QC(I)25/22/20 K7M403625B-QC(I)65/75/80 128Kx36 K 7 N 4 0 3 6 0 1 B - Q C ( I ) 1 6 / 1 3 K7N403609B-QC(I)25/22/20
FlowThrough Pipelined Pipelined FlowThrough Pipelined Pipelined FlowThrough Pipelined Pipelined
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
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November 2001 Rev 1.0
K7N403609B K7N403209B K7N401809B
128Kx36/x32 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 128Kx32 & 256Kx18-Bit Pipelined NtRAMTM
FEATURES
· VDD=3.3V+0.165V/-0.165V Power Supply. · VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. · Byte Writable Function. · Enable clock and suspend operation. · Single READ/WRITE control pin. · Self-Timed Write Cycle. · Three Chip Enable for simple depth expansion with no datacontention. · interleaved burst or a linear burst mode. · Asynchronous output enable control. · Power Down mode. · TTL-Level Three-State Outputs. · 100-TQFP-1420A Package. · Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7N403609B, K7N403209B and K7N401809B are 4,718,592 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. The K7N403609B, K7N403209B and K7N401809B are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -25 4.0 2.4 2.4 -22 4.4 2.6 2.6 -20 5.0 2.8 2.8 Unit ns ns ns
LOGIC BLOCK DIAGRAM
LBO A [0:16]or A [0:17]
ADDRESS
REGISTER
A0~ A 1 A 2 ~ A 1 6 or A2~A 1 7
BURST ADDRESS COUNTER
A 0 ~ A 1 1 2 8 K x 3 6 / 3 2 , 256Kx18 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER
CONTROL
WRITE
ADDRESS REGISTER
K
DATA-IN REGISTER
L O G IC
K
DATA-IN REGISTER
CS1 CS2 CS2 ADV WE BWx
( x = a , b , c , d or a,b)
CO N TRO L R E G IS T E R
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd 3 6 / 3 2 or 18
N t R A M T M and No Turnaround Random Access Memory are trademarks of Samsung,
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November 2001 Rev 1.0
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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