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Part: K7N641831M-FC25
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 64 Mb
-> NtRAM(FT & PP)
Description: Description = K7N641831M ;; Organization = 4Mx18 ;; Operating Mode = - ;; VDD(V) = 1.8,2.5,3.3 ;; Access Time-tCD(ns) = - ;; Speed-tcyc (MHz) = 250,167 ;; I/o Voltage(V) = - ;; Package = 100TQGP,119BGA,165FBGA ;; Production Status = Engineering Sample(4Q,'04) ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7N641831M-FC25 datasheet File size : 282 kB
Request For quote: Find where to buy K7N641831M-FC25
Datasheet text preview:
K7N643631M K7N641831M
Document Title
2Mx36 & 4Mx18-Bit Pipelined NtRAMT M
Preliminary 2Mx36 & 4Mx18 Pipelined NtRAM TM
Revision History
Rev. No. 0.0 0.1 0.2 History 1. Initial document. 1. Delete the speed bins (FT : 7.5ns, 8.5ns / PP : 200MHz) 1 . Corrected Part number (K7N643635M -> K7N643631M) 2 . Change to the New JTAG scan order. 1 . Add the comment about Vdd/Vddq wide by note on page 13. Draft Date Sep. 30. 2002 O c t . 8. 2002 F e b . 25, 2003 Remark Advance Preliminary Preliminary
0.3
M a r . 10, 2003
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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M a r . 2003 R e v 0.3
K7N643631M K7N641831M
Preliminary 2Mx36 & 4Mx18 Pipelined NtRAM TM
64Mb NtRAM (Flow Through / Pipelined) Ordering Information
Org. P a r t Number K7M641835M-Q(H/F)C65 K7N641831M-Q(H/F)C25/16 K7M643635M-Q(H/F)C65 K7N643631M-Q(H/F)C25/16 Mode VDD Speed F T ; Access Time(ns) Pipelined ; Cycle Time(MHz) 6.5ns 250/167MHz 6.5ns 250/167MHz PKG Temp
4Mx18 2Mx36
F l o w T h r o u g h 1.8/2.5/3.3 Pipelined Pipelined 1.8/2.5/3.3 1.8/2.5/3.3 F l o w T h r o u g h 1.8/2.5/3.3
Q:100TQFP C H:119BGA (Commercial F : 1 6 5 F B G A Temperature Range)
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K7N643631M K7N641831M
Preliminary 2Mx36 & 4Mx18 Pipelined NtRAM TM
2Mx36 & 4Mx18-Bit Pipelined NtRAMTM
FEATURES
· 1.8 or 2.5 or 3.3V ±5% Power Supply. · Byte Writable Function. · Enable clock and suspend operation. · Single READ/WRITE control pin. · Self-Timed Write Cycle. · Three Chip Enable for simple depth expansion with no data contention . · A interleaved burst or a linear burst mode. · Asynchronous output enable control. · Power Down mode. · TTL-Level Three-State Outputs. · 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package). · 165FBGA(11x15 ball aray) with body size of 15mmx17mm.
G E N E R A L DESCRIPTION
T h e K7N643631M and K7N641831M are 75,497,472-bits Sync h r o n o u s Static SRAMs. T h e NtRAM TM, or No Turnaround Random Access Memory util i z e s all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output e n a b l e and linear burst order are synchronized to input clock. B u r s t order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising e d g e of the clock input. This feature eliminates complex off-chip write pulse generation a n d provides increased timing flexibility for incoming signals. F o r read cycles, pipelined SRAM output data is temporarily s t o r e d by an edge triggered output register and then released t o the output buffers at the next rising edge of clock. T h e K7N643631M and K7N641831M are implemented with S A M S U N G s high performance CMOS technology and is availa b l e in 100pin TQFP, 119BGA and 165FBGA packages. Multip l e power and ground pins minimize ground bounce.
F A S T ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -25 4.0 2.6 2.6 -16 6.0 3.5 3.5 Unit ns ns ns
LOGIC BLOCK DIAGRAM
LBO ADDRESS R E G I S T E R A 2 ~A 20 or A 2~A 21 A 0~A 1 BURST ADDRESS COUNTER A 0~A 1 2 M x 3 6 , 4Mx18 MEMORY ARRAY
A [0:20]or A [0:21]
CLK CKE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K CS1 CS2 CS2 ADV WE B Wx ( x = a , b , c , d or a,b) OE ZZ D Q a0 ~ DQd7 or D Q a0 ~ DQb8 D Q P a ~ DQPd 3 6 or 18
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
Nt RAM TM and No Turnaround Random Access Memory are trademarks of Samsung.
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