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Part: K7N801809A
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 8 Mb
-> NtRAM(FT & PP)
Description: Description = K7N801809A 512K X 18Bit Pipelined NtRAM™ ;; Organization = 512Kx18 ;; Operating Mode = SPB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 3.5,3.8,4.2,5.0 ;; Speed-tcyc (MHz) = 167,150,133,100 ;; I/o Voltage(V) = 3.3,2.5 ;; Package = 100TQFP,119BGA ;; Production Status = Eol ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7N801809A datasheet File size : 461 kB
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Datasheet text preview:
K7N803609A K7N801809A
Document Title
256Kx36-Bit Pipelined NtRAMTM
256Kx36 & 512Kx18 Pipelined NtRAMTM
Revision History
Rev. No. 0.0 1.0 History 1. Initial document. 1. Final spec Release. 2. Add 119BGA(7x17 Ball Grid Array Package) Draft Date May. 24. 2000 July. 03. 2000 Remark Preliminary Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
July 2000 Rev 1.0
K7N803609A K7N801809A
256Kx36-Bit Pipelined NtRAMTM
FEATURES
256Kx36 & 512Kx18 Pipelined NtRAMTM
GENERAL DESCRIPTION
The K7N803609A and K7N801809A is 9,437,184 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N803609A and K7N801809A is implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP and 119BGA packages. Multiple power and ground pins minimize ground bounce.
· 3.3V+0.165V/-0.165V Power Supply. · I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. · Byte Writable Function. · Enable clock and suspend operation. · Single READ/WRITE control pin. · Self-Timed Write Cycle. · Three Chip Enable for simple depth expansion with no data contention . · interleaved burst or a linear burst mode. · Asynchronous output enable control. · Power Down mode. ·100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -22 4.4 2.8 2.8 -20 5.0 3.2 3.2 - 18 5.4 3.3 3.3 Unit ns ns ns
LOGIC BLOCK DIAGRAM
LBO A [0:17] ADDRESS REGISTER A2~A17 A0~A1
BURST ADDRESS COUNTER
A0~A1 256Kx36 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d) OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd 36
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung, and its architecture and functionalities are supported by NEC and Toshiba.
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July 2000 Rev 1.0
K7N803609A K7N801809A
PIN CONFIGURATION(TOP VIEW)
BWd BWb
256Kx36 & 512Kx18 Pipelined NtRAMTM
BWa
BWc
CKE
ADV
N.C.
CL K
CS1
CS2
CS2
VDD
VSS
WE
A17 83
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
PIN NAME
SYMBOL A0 - A17 PIN NAME Address Inputs TQFP PIN NO. SYMBOL VDD VSS N.C. DQa 0~a7 DQb 0~b7 DQc0~c7 DQd 0~d7 DQPa~Pd VDDQ VSSQ PIN NAME TQFP PIN NO. 32,33,34,35,36,37, 4 4 45,46,47,48,49,50,81 82,83,99,100 ADV Address Advance/Load 85 WE Read/Write Control Input 88 CLK Clock 89 CKE Clock Enable 87 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 BWx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 ZZ Power Sleep Mode 64 LBO Burst Mode Control 31 Power Supply(+3.3V) 14,15,16,41,65,66,91 Ground 17,40,67,90 No Connect 38,39,42,43,84 Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30
LBO
VSS
Output Power Supply 4,11,20,27,54,61,70,77 (3.3V or 2.5V) Output Ground 5,10,21,26,55,60,71,76
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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A16
50
DQPc DQc0 DQc1 VDDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ V SSQ DQd2 DQd3 DQd4 DQd5 V SSQ VDDQ DQd6 DQd7 DQPd
81
A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7N803609A(256Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb7 DQb6 V DDQ V SSQ DQb5 DQb4 DQb3 DQb2 V SSQ V DDQ DQb1 DQb0 V SS VDD VDD ZZ DQa7 DQa6 V DDQ V SSQ DQa5 DQa4 DQa3 DQa2 V SSQ V DDQ DQa1 DQa0 DQPa
July 2000 Rev 1.0
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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