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Part: K7N801809B
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 8 Mb
-> NtRAM(FT & PP)
Description: Description = K7N801809B 256Kx36 & 256Kx32 & 512Kx18 Pipelined NtRAM™ ;; Organization = 512Kx18 ;; Operating Mode = SPB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 2.6,2.8,3.2 ;; Speed-tcyc (MHz) = 250,225,200 ;; I/o Voltage(V) = 3.3,2.5 ;; Package = 100TQFP ;; Production Status = Mass Production ;; Comments = Pipe
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7N801809B datasheet File size : 461 kB
Request For quote: Find where to buy K7N801809B
Datasheet text preview:
K7N803609B K7N803209B K7N801809B
Document Title
256Kx36/x32 & 512Kx18 Pipelined NtRAMT M
256Kx36 & 256Kx32 & 512Kx18-Bit Pipelined NtRAMT M
Revision History
Rev. No. 0.0 0.1 0.2 1.0 History 1. Initial document. 1. Add x32 org part and industrial temperature part 1 . change scan order(1) form 4T to 6T at 119BGA(x18) 1 . Final spec release 2 . Change ISB2 form 50mA to 60mA 1 . Remove tCYC 225MHz(-22) 1 . Delete 119BGA package Draft Date May. 18. 2001 Aug. 11. 2001 Aug. 28. 2001 Nov . 16. 2001 Remark Preliminary Preliminary Preliminary Final
2.0 2.1
A p r i l . 01. 2002 A p r i l . 04. 2003
Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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A p r i l 2003 Rev 2.1
K7N803609B K7N803209B K7N801809B
256Kx36/x32 & 512Kx18 Pipelined NtRAMT M
8Mb NtRAM(Flow Through / Pipelined) Ordering Information
Org. P a r t Number Mode VDD Speed FT ; Access Time(ns) P i p e l i n e d ; Cycle Time(MHz) 6.5/7.5/8.5 ns 1 6 7 / 1 3 3 MHz 2 5 0 / 2 0 0 MHz 1 6 7 / 1 3 3 MHz 2 5 0 / 2 0 0 MHz 6.5/7.5/8.5 ns 1 6 7 / 1 3 3 MHz 2 5 0 / 2 0 0 MHz 1 6 7 / 1 3 3 MHz 2 5 0 / 2 0 0 MHz 6.5/7.5/8.5 ns 1 6 7 / 1 3 3 MHz 2 5 0 / 2 0 0 MHz 1 6 7 / 1 3 3 MHz 2 5 0 / 2 0 0 MHz Q: 100TQFP C: Commercial Temperature Range I: Industrial Temperature Range PKG Temp
K7M801825B-QC(I)65/75/85 K7N801801B-QC(I)16/13 512Kx18 K7N801809B-QC(I)25/20 K7N801845B-QC(I)16/13 K7N801849B-QC(I)25/20 K7M803225B-QC(I)65/75/85 K7N803201B-QC(I)16/13 256Kx32 K7N803209B-QC(I)25/20 K7N803245B-QC(I)C16/13 K7N803249B-QC(I)25/20 K7M803625B-QC(I)65/75/85 K7N803601B-QC(I)16/13 256Kx36 K7N803609B-QC(I)25/20 K7N803645B-QC(I)16/13 K7N803649B-QC(I)25/20
FlowThrough Pipelined Pipelined Pipelined Pipelined FlowThrough Pipelined Pipelined Pipelined Pipelined FlowThrough Pipelined Pipelined Pipelined Pipelined
3.3 3.3 3.3 2.5 2.5 3.3 3.3 3.3 2.5 2.5 3.3 3.3 3.3 2.5 2.5
NOTE : 119BGA is Only Supported with K7N801845B-HC13, K7N803649B-HC25, K7N803601B-HC13 and K7M803625B-HC75.
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A p r i l 2003 Rev 2.1
K7N803609B K7N803209B K7N801809B
256Kx36/x32 & 512Kx18 Pipelined NtRAMT M
256Kx36 & 512Kx18-Bit Pipelined NtRAMTM
FEATURES
· 3.3V+0.165V/-0.165V Power Supply. · I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. · Byte Writable Function. · Enable clock and suspend operation. · Single READ/WRITE control pin. · Self-Timed Write Cycle. · Three Chip Enable for simple depth expansion with no data contention . · interleaved burst or a linear burst mode. · Asynchronous output enable control. · Power Down mode. ·1 0 0 - T Q F P - 1 4 2 0 A · Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
T h e K7N803609B, K7N803209B and K7N801809B are 9 , 4 3 7 , 1 8 4 bits Synchronous Static SRAMs. T h e NtRAMTM , or No Turnaround Random Access Memo r y utilizes all the bandwidth in any combination of operati n g cycles. A d d r e s s , data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". A s y n c h r o n o u s inputs include the sleep mode enable(ZZ). O u t p u t Enable controls the outputs at any given time. W r i t e cycles are internally self-timed and initiated by the r i s i n g edge of the clock input. This feature eliminates comp l e x off-chip write pulse generation a n d provides increased timing flexibility for incoming signals. F o r read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. T h e K7N803609B, K7N803209B and K7N801809B are i m p l e m e n t e d with SAMSUNGs high performance CMOS t e c h n o l o g y and is available in 100pin TQFP and Multiple p o w e r and ground pins minimize ground bounce.
F A S T ACCESS TIMES
PARAMETER C y c l e Time C l o c k Access Time O u t p u t Enable Access Time Symbol tCYC tCD tOE -25 4.0 2.6 2.6 -20 5.0 3.2 3.2 Unit ns ns ns
LOGIC BLOCK DIAGRAM
A [0:17] or A [0:18]
LBO ADDRESS REGISTER A2 ~ A17 or A2~A18 A0~A1
BURST ADDRESS COUNTER
A0 ~A1
256Kx36/32 , 512Kx18 MEMORY ARRAY
CLK CKE CS 1 CS 2 CS 2 ADV WE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
BW x (x=a,b,c,d or a,b) OE ZZ
D Q a0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K
CON TR OL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
36/32 or 18
Nt RAM TM and No Turnaround Random Access Memory are trademarks of Samsung, and its architecture and functionalities are supported by NEC and Toshiba.
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A p r i l 2003 Rev 2.1
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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