|
|
Part: K9K1G08U0M-YCB0
Category:
Memory
-> Flash
-> NAND Flash
-> 1G bit
Description: Description = K9K1G08U0M 128M X 8 Bit NAND Flash Memory ;; Organization = 128Mx8 ;; Operating Voltage(V) = 2.7~3.6 ;; Temperature = C,i ;; Speed(ns) = 50 ;; Package = 48TSOP1 ;; Production Status = Mass Production ;; Comments = 0.15um,Dual Die(512Mb*2)
Company: Samsung Semiconductor, Inc.
Datasheet: Download K9K1G08U0M-YCB0 datasheet File size : 1100 kB
Request For quote: Find where to buy K9K1G08U0M-YCB0
Datasheet text preview:
K9K1G08U0M
Document Title 128M x 8 Bit NAND Flash Memory Revision History
Revision No
0.0 0.1 0.2
FLASH MEMORY
History
1. Initial issue 1.[Page 31] device code (76h) --> device code (79h) 1.Powerup sequence is added : Recovery time of minimum 1µs is required before internal circuit gets ready for any command sequences
Draft Date
Apr. 7th 2001 Jul. 3rd 2001
Remark
Jul. 23th 2001
2.5V VCC High
2.5V
WP
WE
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added. 3. [Page28] Only address A14 to A25 is valid while A9 to A13 is ignored --> Only address A14 to A26 is valid while A9 to A13 is ignored 0.3 (page 30) Sep. 13th 2001 A14 and A15 must be the same between source and target page --> A14 , A15 and A26 must be the same between source and target page New definition of the number of invalid blocks is added. (Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.) Note is added. (VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.) Apr. 4th 2003
0.4
1µ
0.5
Jun. 4th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung' Flash web site. s http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
1
K9K1G08U0M
128M x 8 Bit NAND Flash Memory
FEATURES
· Voltage Supply : 2.7V~3.6V · Organization - Memory Cell Array : (128M + 4,096K)bit x 8bit - Data Register : (512 + 16)bit x8bit multipled by eight planes · Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte · 528-Byte Page Read Operation - Random Access : 12µs(Max.) - Serial Page Access : 50ns(Min.) · Fast Write Cycle Time - Program time : 200µs(Typ.) - Block Erase Time : 2ms(Typ.) · Command/Address/Data Multiplexed I/O Port · Hardware Data Protection - Program/Erase Lockout During Power Transitions · Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years · Command Register Operation · Intelligent Copy-Back Operation · Package : - K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 : 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) · Simultaneous Four Page/Block Program/Erase
FLASH MEMORY
GENERAL DESCRIPTION
The K9K1G08U0M is a 128M(134,217,728)x8bit NAND Flash Memory with a spare 4.096K(4,194,304)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 200µs on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K1G08U0M' extended reliability of 100K program/erase s cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K1G08U0M-YCB0/YIB0 is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
PIN CONFIGURATION
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP R/B VCC VSS N.C Pin Function Data Input/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ready/Busy output Power(+2.7V~3.6V) Ground No Connection
48-pin TSOP1 Standard Type 12mm x 20mm
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
2
K9K1G08U0M
Figure 1. Functional Block Diagram
VCC VSS A9 - A26 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
FLASH MEMORY
1,024M + 32M Bit NAND Flash ARRAY (512 + 16)Byte x 262,144 Page Register & S/A
A0 - A7
A8
Command Command Register
Y-Gating
I/O Buffers & Latches
VCC VSS Output Driver I/0 0 I/0 7
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
CLE ALE WP
Figure 2. Array Organization
1 Block = 32 Pages (16K + 512) Byte
256K Pages (=8,192 Blocks)
1st half Page Register (=256 Bytes)
2nd half Page Register (=256 Bytes)
1 Page = 528 Bytes 1 Block = 528 B x 32 Pages = (16K + 512) Bytes 1 Device = 528B x 32Pages x 8,192 Blocks = 1,056 Mbits 8 bit 16 Bytes
512B Bytes
Page Register
512 Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25 I/O 1 A1 A10 A18 A26 I/O 2 A2 A11 A19 *L 16 Bytes I/O 3 A3 A12 A20 *L
I/O 0 ~ I/O 7
I/O 4 A4 A 13 A 21 *L
I/O 5 A5 A 14 A 22 *L
I/O 6 A6 A15 A23 *L
I/O 7 A7 A16 A24 *L Column Address Row Address (Page Address)
NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low". * The device ignores any additional input of address cycles than reguired.
3
Others parts begin by k9
K9-1 K9-2 K9-3
|
|
|
