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Details, datasheet, quote on part number:KM23V4100DET
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| Part: | KM23V4100DET |
| Category: | Memory => ROM => Mask ROM => Standard => 4M bit |
| Description: | Description = KM23V4100D 4M-Bit (512K X 8 / 256K X 16) CMOS Mask ROM ;; Organization = 512Kx8,256Kx16 ;; Voltage(V) = 3.3 ;; Speed(ns) = 100 ;; Package = 44TSOP2,40DIP,40SOP ;; Current (mA/uA) = 20,25/30 ;; Production Status = Mass Production ;; Comments = Eol BY Dec.'03 |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KM23V4100DET datasheet File size : 74 kB |
| Request For quote: | Find where to buy KM23V4100DET
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Datasheet text preview:
KM23V4100D(E)T
4M-Bit (512Kx8 /256x16) CMOS MASK ROM
FEATURES
· Switchable organization 524,288 x 8(byte mode) 262,144 x 16(word mode) · Fast access time 3.3V Operation : 100ns(Max.) 3.0V Operation : 120ns(Max.) · Supply voltage : single +3.0V/ single +3.3V · Current consumption Operating : 25mA(Max.) Standby : 30µA(Max.) · Fully static operation · All inputs and outputs TTL compatible · Three state outputs · Package -. KM23V4100D(E)T : 44-TSOP2-400
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23V4100D(E)T is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 524,288 x 8 bit(byte mode) or as 262,144 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device operates with 3.0V or 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V4100D(E)T is packaged in a 44-TSOP2.
FUNCTIONAL BLOCK DIAGRAM
A17
PRODUCT INFORMATION
Product Operating Temp 0°C~70°C -20°C~85 °C Vcc Range 3.3V/3.0V Speed (ns) 100/120
. . . . . . . .
A0 A-1
X BUFFERS AND DECODER
MEMORY CELL MATRIX (262,144x16/ 524,288x8)
KM23V4100DT KM23V4100DET
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS
PIN CONFIGURATION
...
CE OE BHE CONTROL LOGIC Q 0 /Q8 Q7/Q 15
N.C N.C A 17 A7 A6 A5 A4 A3 A2
1 2 3 4 5 6 7 8 9 11
44 N.C 43 N.C 42 A 8 41 A 9 40 A10 39 A11 38 A 12 37 A 13 36 A14 35 A15 34 A16
Pin Name A0 - A17 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS N.C
Pin Function Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power Ground No Connection
A1 10 A0 C E 12 V S S 13 OE 14 Q0 Q8 15 16
TSOP2
33 B H E 32 V S S 31 Q15/A-1 30 Q7 29 Q14 28 Q 6 27 Q13 26 Q5 25 Q12 24 Q 4 23 V C C
Q 1 17 Q 9 18 Q2 Q 10 19 20
Q3 21 Q 1 1 22
KM23V4100D(E)T
KM23V4100D(E)T
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Operating Temperature Symbol VIN TBIAS T STG TA Rating -0.3 to +4.5 -10 to +85 -55 to +150 0 to +70 -20 to +85
CMOS MASK ROM
Unit V °C °C °C °C Remark KM23V4100DT KM23V4100DET
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7/3.0 0 Typ 3.0/3.3 0 Max 3.3/3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level SymICC ISB1 ISB2 ILI ILO VIH VIL V OH V OL IOH=-400µA IOL=2.1mA Test Conditions CE =OE=VIL, all outputs open VCC=3.3±0.3V VCC=3.0±0.3V Min 2.0 -0.3 2.4 Max 25 20 500 30 10 10 VCC+0.3 0.6 0.4 Unit mA mA µA µA µA µA V V V V
CE =VIH, all outputs open CE =VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L OE X H BHE X X H L L L Q15/A -1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q 15 : Dout Q0~Q 7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol C OUT CIN Test Conditions VOUT=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
KM23V4100D(E)T
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
0.45V to 2.4V 10ns 1.5V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tOE tDF t OH 0 VCC=3.3V±0.3V Min 100 100 100 50 20 0 Max VCC=3.0V±0.3V Min 120 120 120 60 20 Max Unit ns ns ns ns ns ns
TIMING DIAGRAM
READ
ADD A0~A17 A-1(*1) tACE CE/ CE tOE OE/O E
ADD1 tRC
ADD2 tDF(*3)
tOE
tOH D OUT D0~D7 D8~D15(*2) VALID DATA VALID DATA
NOTES : *1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL) *2. Word Mode only.(BHE = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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