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Details, datasheet, quote on part number:KM23V4200D-10
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| Part: | KM23V4200D-10 |
| Category: | Memory => ROM => Mask ROM => Standard => 4M bit |
| Description: | Description = KM23V4200D 4M-Bit (256K X 16) CMOS Mask ROM ;; Organization = 256Kx16 ;; Voltage(V) = 3.3 ;; Speed(ns) = 120,100 ;; Package = 40DIP ;; Current (mA/uA) = 20,25/30 ;; Production Status = Mass Production ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KM23V4200D-10 datasheet File size : 74 kB |
| Request For quote: | Find where to buy KM23V4200D-10
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Datasheet text preview:
KM23V4200D
4M-Bit (256Kx16) CMOS MASK ROM (EPROM TYPE)
FEATURES
· 262,144 x 16 bit organization · Fast access time 3.3V Operation : 100ns(Max.) 3.0V Operation : 120ns(Max.) · Supply voltage : single +3.0V/ single +3.3V · Current consumption Operating : 25mA(Max.) Standby : 30µA(Max.) · Fully static operation · All inputs and outputs TTL compatible · Three state outputs · Package -. KM23V4200D : 40-DIP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23V4200D is a fully static mask programmable ROM organized 262,144 x 16 bit. It is fabricated using silicon gate CMOS process technology. This device operates with 3.0V or 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V4200D is packaged in a 40-DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A17
. . . . . . . .
A0
X BUFFERS AND DECODER
MEMORY CELL MATRIX (262,144x16)
N.C CE Q15 Q14 1 2 3 4 5 6 7 8 9 40 VCC 39 A 17 38 A 1 6 37 A 15 36 A14
Y BUFFERS AND DECODER
SENSE AMP. BUFFERS
Q 13 Q 12 Q 11 Q10 Q9
35 A 13 34 33 A12 A1 1
32 A 10
...
CE OE
Q 8 10 V S S 11 Q7 12
DIP
31 A 9 30 29 VSS A8
CONTROL LOGIC
Q0
Q 15
Q 6 13 Q5 14 Q4 15
28 A 7 27 A 6 26 A5 25 A 4 24 A 3 23 A 2 22 A 1 21 A0
Q 3 16 Q 2 17 Q1 Q0 18 19
Pin Name A0 - A17 Q0 - Q15 CE OE VCC V SS N.C
Pin Function Address Inputs Data Outputs Chip Enable Output Enable Power Ground No Connection
OE 20
KM23C4200D
KM23V4200D
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG
CMOS MASK ROM
Rating -0.3 to +4.5 -10 to +85 -55 to +150 Unit V °C °C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7/3.0 0 Typ 3.0/3.3 0 Max 3.3/3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH V OL IOH=-400µA IOL=2.1mA Test Conditions CE=OE =VIL, all outputs open VCC=3.3±0.3V VCC=3.0±0.3V Min 2.0 -0.3 2.4 Max 25 20 500 30 10 10 VCC+0.3 0.6 0.4 Unit mA mA µA µA µA µA V V V V
CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L OE X H L Mode Standby Operating Operating Data High-Z High-Z Dout Power Standby Active Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
KM23V4200D
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
Value 0.45V to 2.4V 10ns 1.5V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tOE tDF tOH 0 VCC=3.3V±0.3V Min 100 100 100 50 20 0 Max VCC=3.0V±0.3V Min 120 120 120 60 20 Max Unit ns ns ns ns ns ns
TIMING DIAGRAM
READ
ADD
ADD1 tRC tACE
ADD2 tDF(Note)
CE tOE OE tOH D OUT VALID DATA VALID DATA tAA
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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