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Details, datasheet, quote on part number:KM23V64005AG
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| Part: | KM23V64005AG |
| Category: | Memory => ROM => Mask ROM => Pagemode => 64M bit |
| Description: | Description = KM23V64005A 64M-Bit(8Mx16 / 4Mx16) CMOS Mask ROM ;; Organization = 8Mx8,4Mx16 ;; Voltage(V) = 3.3 ;; Speed(ns) = 100(30) ;; Package = 44SOP,48TSOP1 ;; Current (mA/uA) = 50,60/30 ;; Production Status = Eol ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KM23V64005AG datasheet File size : 90 kB |
| Request For quote: | Find where to buy KM23V64005AG
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Datasheet text preview:
KM23V64005AG
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
FEATURES
· Switchable organization 8,388,608 x 8(byte mode) 4,194,304 x 16(word mode) · Fast access time Random Access Time/Page Access Time 3.3V Operation : 100/30ns(Max.) 3.0V Operation : 120/40ns(Max.) 8 Words / 16 Bytes page access · Supply voltage : single +3.0V/ single +3.3V · Current consumption Operating : 60mA(Max.) Standby : 30µA(Max.) · Fully static operation · All inputs and outputs TTL compatible · Three state outputs · Package KM23V64005AG : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23V64005AG is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 8,388,608 x 8 bit(byte mode) or as 4,194,304 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 8 words (or 16 bytes) of data to read fast in the same page, CE and A3 ~ A21 should not be changed. This device operates with 3.0V or 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V64005AG is packaged in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A21 . . . . . . . . A3 A0~A2 A-1
X BUFFERS AND DECODER
MEMORY CELL MATRIX (4,194,304x16/ 8,388,608x8)
A21 A 18 A17 A7 A6
1 2 3 4 5 6 7 8 9
44 A20 43 A 1 9 42 A8 41 A 9 40 A 1 0 39 A11 38 A 12 37 A 13 36 A14 35 A 15 34 A 1 6 33 BHE 32 VSS 31 Q15/A-1 30 Q 7 29 Q14 28 Q 6 27 Q13 26 Q5 25 Q12 24 Q 4 23 VCC
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS ...
A5 A4 A3 A2
A1 10 A0 11 C E 12 VSS 13 OE 14
SOP
CE OE BHE CONTROL LOGIC Q 0 /Q8 Q 7 /Q1 5
Q0 Q8
15 16
Q 1 17 Q 9 18 Q2 19 20
Pin Name A0 - A2 A3 - A21 Q0 - Q14 Q15 /A-1 BHE CE OE V CC VSS
Pin Function Page Address Inputs Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power Ground
Q10
Q3 21 Q11 22
KM23V64005AG
KM23V64005AG
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN T BIAS T STG Rating
CMOS MASK ROM
Unit V °C °C
-0.3 to +4.5 -10 to +85 -55 to +150
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7/3.0 0 Typ 3.0/3.3 0 Max 3.3/3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH V IL VOH VOL IOH=-400 µA IOL=2.1mA Test Conditions CE=OE =VIL, all outputs open VCC=3.3V±0.3V VCC=3.0V±0.3V Min Max 60 50 500 30 2.0 -0.3 2.4 10 10 VCC+0.3 0.6 0.4 Unit mA mA µA µA µA µA V V V V
CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L L OE X H L BHE X X H L Q15/A-1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q15 : Dout Q0~Q7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol C OUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
KM23V64005AG
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value 0.45V to 2.4V 10ns 1.5V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Page Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change
NOTE : Page Address is determined as below. Word mode (BHE=VIH) : A0, A1, A2 Byte mode (BHE=VIL) : A-1, A0, A1, A2
Symbol t RC tACE tAA tPA t OE tDF tOH
VCC=3.3V±0.3V Min 100 100 100 30 30 20 0 Max
VCC=3.0V±0.3V Min 120 120 120 40 40 20 0 Max
Unit ns ns ns ns ns ns ns
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