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Details, datasheet, quote on part number:KM44C4005C
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Datasheet text preview:
KM44C4005C, KM44C4105C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode. This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsungs advanced CMOS process to realize high bandwidth, low power consumption and high reliability.
FEATURES
· Part Identification - KM44C4005C/C-L (5V, 4K Ref.) - KM44C4105C/C-L (5V, 2K Ref.)
· Extended Data Out mode operation (Fast Page Mode with Extended Data Out) · Four separate CAS pins provide for separate I/O operation · CAS-before-RAS refresh capability · RAS-only and Hidden refresh capability · Self-refresh capability (L-ver only) · Fast parallel test mode capability Unit : mW · TTL compatible inputs and outputs · Early Write or output enable controlled write · JEDEC Standard pinout · Available in Plastic SOJ and TSOP(II) packages · Single +5V±10% power supply
· Active Power Dissipation Speed -5 -6 Refresh Cycle 4K 495 440 2K 605 550
FUNCTIONAL BLOCK DIAGRAM
· Refresh Cycles Part NO. C4005C C4105C Refresh cycle 4K 2K Refresh period Normal 64ms 32ms L-ver 128ms
Refresh Timer Refresh Control Row Decoder Sense Amps & I/O RAS CAS 0 - 3 W Control Clocks Vcc Vss
VBB Generator
Data in Buffer
· Performance Range Speed -5 -6
Refresh Counter
tRAC
50ns 60ns
tCAC
13ns 15ns
tRC
84ns 104ns
tHPC
20ns 25ns
Memory Array 4,194,304 x 4 Cells
DQ0 to DQ3
A0-A11 (A0 - A10) *1 A0 - A9 (A0 - A10) *1
Row Address Buffer Col. Address Buffer Column Decoder
Data out Buffer OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM44C4005C, KM44C4105C
CMOS DRAM
PIN CONFIGURATION (Top Views)
·KM44C40(1)05CK
·KM44C40(1)05CS
VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS
VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS
*A11 is N.C for KM44C4105C(5V, 2K Ref. product) K : 300mil 28 SOJ S : 300mil 28 TSOP II
Pin Name A0 - A11 A0 - A10 DQ0 - 3 VSS RAS CAS0~CAS3 W OE VCC N.C
Pin Function Address Inputs (4K Product) Address Inputs (2K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) No Connection
KM44C4005C, KM44C4105C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS Rating -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50
CMOS DRAM
Units V V °C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0
*2
Typ 5.0 0 -
Max 5.5 0 VCC+1.0 0.8
*1
Units V V V V
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC *2 : -2.0/20ns, Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVIN+0.5V, all other input pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V
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