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Details, datasheet, quote on part number:KM44L32031BT-GF0
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Datasheet text preview:
128Mb DDR SDRAM
Target
DDR SDRAM Specification Version 0.61
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REV. 0.61 August 9. '99
128Mb DDR SDRAM
Revision History
Version 0 (May, 1998) - First version for internal review Version 0.1(June, 1998) - Added x4 organization Version 0.2(Sep,1998) 1. Added "Issue prcharge command for all banks of the device" as the fourth step of power-up squence. 2. In power down mode timing diagram, NOP condition is added to precharge power down exit. Version 0.3(Dec,1998) - Added QFC Function. - Added DC current value - Reduce I/O capacitance values Version 0.4(Feb,1999) -Added DDR SDRAM history for reference(refer to the following page) -Added low power version DC spec Version 0.5(Apr,1999) -Revised following first showing for JEDEC standard -Added DC target current based on new DC test condition Version 0.6(July 1,1999) 1.Modified binning policy From To -Z (133Mhz) -Z (133Mhz/266Mbps@CL=2) -8 (125Mhz) -Y (133Mhz/266Mbps@CL=2.5) -0 (100Mhz) -0 (100Mhz/200Mbps@CL=2) 2.Modified the following AC spec values From. -Z tAC tDQSCK tDQSQ tDS/tDH t C D L R *1 tPRE
*1
Target
To. -0 +/- 1ns +/- 1ns +/- 0.75ns 0.75 ns 2.5tCK-tDQSS 1tCK +/- 1ns tCK/2 +/- 1ns tCK/2 +/- 1ns -Z +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -Y +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -0 +/- 0.8ns +/- 0.8ns +/- 0.6ns 0.6 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/-0.8ns
+/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 2.5tCK-tDQSS 1tCK +/- 0.75ns tCK/2 +/- 0.75ns tCK/2 +/- 0.75ns
t R P S T *1 tHZQ
*1 *1
: Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol From. To. tDQCK tAC Output data access time from CK/CK Version 0.61(August 9,1999) - Changed the some values of "write with auto precharge" table for different bank in page 30. Asserted command Old Read Read + AP*1 Legal Legal For Different Bank 3 New Illegal Illegal Old Legal Legal 4 New Illegal Illegal
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REV. 0.61 August 9. '99
128Mb DDR SDRAM
Revision History
-This revision history is for 64Mb and only for reference in other density.
Target
Version 0.5 (JUN, 1997) - First version for external release - Center aligned DQ on reads and writes, 3.3V Vdd/Vddq, LVTTL for command and SSTL for DQ, DQS, CK and DM. Version 0.6 (SEP. 1997) - Changed to Edge alignedDQ on reads - Add detailed discription for each functionality Version 0.7 (JAN. 1998) - Power supply: 3.3V +10%,-5% power supply for device operation (Vdd) 2.5V Power supply for I/O interface (Vddq) - Interface: Add SSTL_2 for CK/DM (class I), DQ/DQS(class II) for KM416H431T. * Put two part numbers, KM416H430T and KM416H431T. - Clock input: Change to differential clock from single ended clock. * Use CK, CK instead of CLK. - Package: Change to 66pin TSOP-II, instead of 54pin TSOP-II - tDQSS: Change to 0.75 ~ 1.25 tCK form 3ns ~ 1 tCK. Add tSDQS(DQS-in setup time) - In page 13, "DM can be ~" is modified to "DM must be ~". - Tighten AC specs Change CK/CK hign/low level width from 0.4(min)/0.6(max)tCK to 0.45(min)/0.55(max)tCK. -> Better input clock duty ratio from differential clock. Version 0.8 (FEB. 1998) - Correct pin rotation on pin 48 and 49 from 48-Vref, 49-Vss to 48-Vss, 49-Vref. Version 0.9 (MAR. 1998) - Change power-up sequence . Add EMRS for DLL enable/disable . Change DLL reset pin from A9 to A8 on MRS. - Change speed range . Add 133Mhz (266Mbps/pin), remove -12 (83Mhz) - Change output load circuit - Change input capacitance - Add a comment on read interrupting write timing: Read command interrupting write can not be issued at the next clock edge of write command. - Modify the simplified state diagram on page 24. Version 0.91 (May, 1998) - Changed part number from KM416H430T/KM416H431T to KM416H4030T/KM416H4031T - Added the 66pin package dimension on page 30. - Changed Output Load Circuit 2 in page 29 - Removed CL=1.5 - Corrected typos
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REV. 0.61 August 9. '99
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