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Details, datasheet, quote on part number:KM48S8030C
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Datasheet text preview:
KM48S8030C
Revision History
Revision 0.0 (Oct., 1998)
· PC133 first published.
Preliminary PC133 CMOS SDRAM
REV. 0 Oct. '98
KM48S8030C
2M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
· · · · JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle)
Preliminary PC133 CMOS SDRAM
GENERAL DESCRIPTION
The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
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ORDERING INFORMATION
Part No. KM48S8030CT-G/FA Max Freq. 133MHz (CL 3) Interface Package LVTTL 54 TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE LDQM
Data Input Register
Bank Select 2M x 8 Sense AMP 2M x 8 2M x 8 2M x 8 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
Programming Register LWCBR LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM * Samsung Electronics reserves the right to change products or specification without notice.
REV. 0 Oct. '98
KM48S8030C
PIN CONFIGURATION (Top view)
VD D DQ0 VD D Q N.C DQ1 VSSQ N.C DQ2 VD D Q N.C DQ3 VSSQ N.C VD D N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ N.C DQ6 VD D Q N.C DQ5 VSSQ N.C DQ4 VD D Q N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
Preliminary PC133 CMOS SDRAM
54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM DQ 0 ~ 7 VDD/VSS VDDQ/VSSQ N.C/RFU
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
REV. 0 Oct. '98
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