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Part: KM48S8030D
Category:
Memory
-> DRAM
-> DDR SDRAM
Description: 64mbit Sdram 2m X 8bit X 4 Banks Synchronous DRAM LVTTL
Company: Samsung Semiconductor, Inc.
Datasheet: Download KM48S8030D datasheet File size : 2120 kB
Request For quote: Find where to buy KM48S8030D
Datasheet text preview:
KM48S8030D
C M O S SDRAM
64Mbit SDRAM
2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.0 May 1999
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 May 1999
KM48S8030D
R e v i s i o n History
R e v i s i o n 0.0 (May 15, 1999)
C M O S SDRAM
· Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER. · Skip ICC4 value of CL=2 in DC characteristics in datasheet. · Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER. · Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE. · Symbol Change Notice
II L II L IO L Before Input leakage current (inputs) Input leakage current (I/O pins) Output open @ DC characteristic table IL I Io After Input leakage current Output open @ DC characteristic table
· Test Condition in DC CHARACTERISTIC Change Notice
Symbol IC C 2 P , I C C 3 P IC C 2 N , I C C 3 N IC C 4 Before CKE VIL(max), tCC = 15ns CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns 2 Banks activated After CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns 4 Banks activated
Rev. 0.0 May 1999
KM48S8030D
2 M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
· · · · JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle)
C M O S SDRAM
G E N E R A L DESCRIPTION
The KM48S8030D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
· · · · ·
O R D E R I N G INFORMATION
P a r t No. KM48S8030DT-G/FA KM48S8030DT-G/F8 KM48S8030DT-G/FH KM48S8030DT-G/FL M a x Freq. 133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54 TSOP(II) Interface Package
F U N C T I O N A L BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select 2M x 8 Sense AMP 2M x 8 2M x 8 2M x 8 R efresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
L RA S
L CB R
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 May 1999
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