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Part: KM48V8000BK
Category:
Memory
-> DRAM
-> Async DRAM
-> 64 Mb
Description: Description = KM48V8000BK 8M X 8bit CMOS Dynamic RAM With Fast Page Mode ;; Organization = 8Mx8 ;; Mode = Fast Page ;; Voltage(V) = 3.3 ;; Refresh = 8K/64ms ;; Speed(ns) = 50,60 ;; Package = 32SOJ,32TSOP2 ;; Power = Normal,low ;; Production Status = Eol ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download KM48V8000BK datasheet File size : 2120 kB
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Datasheet text preview:
KM48V8000B, KM48V8100B
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
· Part Identification - KM48V8000B/B-L(3.3V, 8K Ref.) - KM48V8100B/B-L(3.3V, 4K Ref.) · Active Power Dissipation Unit : mW Speed -45 -5 -6 · Refresh Cycles Part NO. KM48V8000B* KM48V8100B Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms
RAS CAS W
· Fast Page Mode operation · CAS-before-RAS refresh capability · RAS-only and Hidden refresh capability · Self-refresh capability (L-ver only) · Fast parallel test mode capability · LVTTL(3.3V) compatible inputs and outputs · Early Write or output enable controlled write · JEDEC Standard pinout · Available in Plastic SOJ and TSOP(II) packages · +3.3V±0.3V power supply 4K 468 432 396
8K 360 324 288
FUNCTIONAL BLOCK DIAGRAM
Control Clocks Vcc Vss
VBB Generator
Refresh Control Refresh Counter Memory Array 8,388,608 x 8 Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) · Performance Range Speed -45 -5 -6
Refresh Timer
Row Decoder Data in Buffer DQ0 to DQ7 Data out Buffer OE
tRAC
45ns 50ns 60ns
tCAC
12ns 13ns 15ns
tRC
80ns 90ns 110ns
tPC
31ns 35ns 40ns
A0~A12 (A0~A11)*1 A0~A9 (A0~A10)*1
Row Address Buffer Col. Address Buffer Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM48V8000B, KM48V8100B
CMOS DRAM
PIN CONFIGURATION (Top Views)
·KM48V80(1)00BK
·KM48V80(1)00BS
VCC DQ0 DQ1 DQ2 DQ3 N.C VCC W RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS DQ7 DQ6 DQ5 DQ4 VSS CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
VCC DQ0 DQ1 DQ2 DQ3 N.C VCC W RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS DQ7 DQ6 DQ5 DQ4 VSS CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(K : 400mil SOJ)
(S : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name A0 - A12 A0 - A11 DQ0 - 7 VSS RAS CAS W OE VCC N.C
Pin Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection
KM48V8000B, KM48V8100B
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Tstg PD IOS Rating -0.5 to +6.5 -0.5 to +4.6 -55 to +150 1 50
CMOS DRAM
Units V V °C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3
*2
Typ 3.3 0 -
Max 3.6 0 +5.5
*1
Units V V V V
0.8
*1 : 6.5V at pulse width15ns which is measured at VCC *2 : -1.3 at pulse width15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V
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