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Part: KM68V4002BLI-15
Category:
Memory
-> SRAM
-> Async. SRAM
-> 4 Mb
-> -> Fast SRAM
Description: Description = KM68V4002B 512K X 8 Bit High Speed CMOS Static RAM(3.3V Operating) ;; Organization = 512Kx8 ;; Vcc(V) = 3.3 ;; Speed-tAA(ns) = 10,12,15 ;; Operating Temperature = C,i ;; Operating Current(mA) = 205 ;; Standby Current(mA) = 10/1.2 ;; Package = 36SOJ,36TSOP2,44TSOP2 ;; Production Status = Eol ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download KM68V4002BLI-15 datasheet File size : 32 kB
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Datasheet text preview:
PRELIMINARY
KM68V4002B/BL, KM68V4002BI/BLI
Document Title
512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Add 30pF capacitive in test load. 2.3. Relax DC characteristics. Item Previous ICC 10ns 170mA 12ns 160mA 15ns 150mA I SB f=max. 40mA I SB1 f=0 10 / 1mA IDR VDR=3.0V 0.9mA Draft Data Jan. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary
Rev. 2.0
Feb.11th.1998
Final
Current 205mA 200mA 195mA 50mA 10 / 1.2mA 1.0mA Jun.27th 1998 Final
Rev. 2.1
Change operating current at Industrial Temperature range. Previous spec. Changed spec. Items (10/12/15ns part) (10/12/15ns part) Icc 205/200/195mA 230/225/220mA
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.1 June 1998
PRELIMINARY
KM68V4002B/BL, KM68V4002BI/BLI
512K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
· Fast Access Time 10,12,15ns(Max.) · Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS) : 10mA(Max.) 1.2mA(Max.)- L-Ver. Operating KM68V4002B/BL - 10 : 205mA(Max.) KM68V4002B/BL - 12 : 200mA(Max.) KM68V4002B/BL - 15 : 195mA(Max.) · Single 3.3 ±0.3V Power Supply · TTL Compatible Inputs and Outputs · Fully Static Operation - No Clock or Refresh required · Three State Outputs · 2V Minimum Data Retention ; L-Ver. only · Center Power/Ground Pin Configuration · Standard Pin Configuration KM68V4002BJ : 36-SOJ-400 KM68V4002BT : 36-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The KM68V4002B is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. The KM68V4002B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68V4002B is packaged in a 400 mil 36-pin plastic SOJ or TSOP(II) forward.
PIN CONFIGURATION(Top View)
A0 A1 A2
1 2 3 4 5 6 7 8 9 10
3 6 N.C 3 5 A 18 3 4 A 17 3 3 A 16 3 2 A 15 3 1 OE 3 0 I/O8
ORDERING INFORMATION
KM68V4002B/BL -10/12/15 KM68V4002BI/BLI -10/12/15 Commercial Temp. Industrial Temp.
A3 A4 CS I/O1 I/O2
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1~I/O8
Vcc Vss
SOJ/ TSOP2
2 9 I/O7 2 8 Vss 2 7 Vcc 2 6 I/O6 2 5 I/O5 2 4 A 14 2 3 A 13 2 2 A 12 2 1 A 11 2 0 A 10 1 9 N.C
Pre-Charge Circuit
I/O3 11 I/O4 12 WE A5 13 14 15 16 17 18
Row Select
Memory Array 512 Rows 1024x8 Columns
A6 A7 A8 A9
Data Cont. CLK Gen.
I/O Circuit Column Select
PIN FUNCTION
Pin Name A0 - A18 WE Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground No Connection
A10 A12 A14 A16 A18 A9 A11 A13 A15 A17
CS OE
CS WE OE
I/O1 ~ I/O8 VCC VSS N.C
-2-
Rev 2.1 June 1998
PRELIMINARY
KM68V4002B/BL, KM68V4002BI/BLI
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC PD TSTG TA TA Rating -0.5 to 4.6 -0.5 to 4.6 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W °C °C °C
CMOS SRAM
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC V SS VIH VIL Min 3.0 0 2.0 -0.3** Typ 3.3 0 Max 3.6 0 VCC+0.3*** 0.8 Unit V V V V
* The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 8ns) for I 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width 8ns) for I 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol I LI ILO ICC VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA 10ns 12ns 15ns Standby Current ISB ISB1 Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN 0.2V IOL=8mA IOH=-4mA Normal L-Ver. Test Conditions Min -2 -2 2.4 Max 2 2 205 200 195 50 10 1.2 0.4 V V mA mA Unit µA µA mA
Output Low Voltage Level Output High Voltage Level
VOL V OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol CI/O CIN
Test Conditions VI/O=0V VIN=0V
MIN -
Max 8 7
Unit pF pF
-3-
Rev 2.1 June 1998
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