|
Details, datasheet, quote on part number:KM736S949H
| |
| Part: | KM736S949H |
| Category: | Memory => SRAM => Sync. SRAM => 16 Mb => NtRAM(FT & PP) |
| Description: | Description = KM736S949H 512Kx36 & 1Mx18 Pipelined NtRAM™ ;; Organization = 512Kx36 ;; Operating Mode = SPB ;; VDD(V) = 2.5 ;; Access Time-tCD(ns) = 3.5,3.8,4.2,5.0 ;; Speed-tcyc (MHz) = 167,150,133,100 ;; I/o Voltage(V) = 2.5 ;; Package = 100TQFP,119BGA ;; Production Status = Eol ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KM736S949H datasheet File size : 470 kB |
| Request For quote: | Find where to buy KM736S949H
|
| |
Datasheet text preview:
KM736S949 KM718S049
Document Title
512Kx36 & 1Mx18 Pipelined NtRAMTM
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
Revision History
Rev. No. 0.0 0.1 0.2 History 1. Initial document. 1. Update ICC & ISB values. 1. Change pin allocation at 119BGA . - A4 ; from NC to A . - B2 ; from A to CS2 - B4 ; from CKE to ADV - B6 ; from A to CS2 - G4 ; from ADV to A - H4 ; from NC to WE - M4 ; from WE toCKE 2. Changed DC condition at Icc and parameters Icc ; from 320mA to 300mA at -67, from 300mA to 280mA at -75, Add tCYC 167MHz. Finl spec release Draft Date Dec. 22. 1998 May. 27. 1999 Nov. 19. 1999 Remark Preliminary Preliminary Preliminary
0.3 1.0
Nov. 26. 1999 Jan. 28. 2000
Preliminary Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
January 2000 Rev 1.0
KM736S949 KM718S049
512Kx36 & 1Mx18 Pipelined NtRAMTM
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
FEATURES
· 2.5V ±5% Power Supply. · Byte Writable Function. · Enable clock and suspend operation. · Single READ/WRITE control pin. · Self-Timed Write Cycle. · Three Chip Enable for simple depth expansion with no datacontention . · A interleaved burst or a linear burst mode. · Asynchronous output enable control. · Power Down mode. · 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
GENERAL DESCRIPTION
The KM736S949 and KM718S049 are 18,874,368-bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The KM736S949 and KM718S049 are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP and 119BGA packages. Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time S y m b o l -60 -67 -75 -10 U n i t tCYC tCD tOE 6.0 6.7 7.5 10 ns ns ns
3.5 3.8 4.2 5.0 3.5 3.8 4.2 5.0
LOGIC BLOCK DIAGRAM
LBO A [0:18]or A [0:19] ADDRESS REGISTER A2~A18 or A2~A19 A0~A1 BURST ADDRESS COUNTER A0~A1 512Kx36, 1Mx18 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd 36 or 18
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.
-2-
January 2000 Rev 1.0
KM736S949 KM718S049
PIN CONFIGURATION(TOP VIEW)
BWd BWb BWa BWc
512Kx36 & 1Mx18 Pipelined NtRAMTM
CKE
ADV
CL K
CS1
CS2
CS2
VDD
VSS
WE
A18
A17 83
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
PIN NAME
SYMBOL A0 - A18 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,44 4 5 , 4 6 , 4 7 , 4 8 , 4 9 , 50,81 82,83,84,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL V DD V SS N.C. D Q a 0~ a 7 D Q b 0~ b 7 D Q c 0~c7 D Q d 0~ d 7 DQPa~Pd V DDQ V SSQ PIN NAME Power Supply(2.5V) Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs TQFP PIN NO. 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30
ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
LBO
VSS
Output Power Supply 4,11,20,27,54,61,70,77 (2.5V) Output Ground 5,10,21,26,55,60,71,76
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-3-
A16
50
DQPc DQc0 DQc1 VDDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ V SSQ DQd2 DQd3 DQd4 DQd5 V SSQ VDDQ DQd6 DQd7 DQPd
81
A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
KM736S949(512Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb7 DQb6 V DDQ V SSQ DQb5 DQb4 DQb3 DQb2 V SSQ V DDQ DQb1 DQb0 V SS VDD VDD ZZ DQa7 DQa6 V DDQ V SSQ DQa5 DQa4 DQa3 DQa2 V SSQ V DDQ DQa1 DQa0 DQPa
January 2000 Rev 1.0
|
|
