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Details, datasheet, quote on part number:KM736V687T
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| Part: | KM736V687T |
| Category: | Memory => SRAM => Sync. SRAM => 2 Mb => SB & SPB |
| Description: | Description = KM736V687T 64Kx36-Bit Synchronous Burst SRAM ;; Organization = 64Kx36 ;; Operating Mode = FT(SB) ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 8.5,9.0,10.0 ;; Speed-tcyc (MHz) = 83,66,60 ;; I/o Voltage(V) = 3.3 ;; Package = 100TQFP ;; Production Status = Eol ;; Comments = Design is Not Recommended |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KM736V687T datasheet File size : 469 kB |
| Request For quote: | Find where to buy KM736V687T
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Datasheet text preview:
PRELIMINARY
KM736V687
Document Title
64Kx36-Bit Synchronous Burst SRAM, 3.3V Power Datasheets for 100TQFP
64Kx36 Synchronous SRAM
Revision History
Rev. No.
Rev. 0.0 Rev. 1.0
History
Initial draft Final spec release
Draft Date
Nov. 02. 1996 May. 27. 1997
Remark
Preliminary Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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May 1997 Rev 1.0
PRELIMINARY
KM736V687
64Kx36-Bit Synchronous Burst SRAM
FEATURES
Synchronous Operation. On-Chip Address Counter. Write Self-Timed Cycle. On-Chip Address and Control Registers. Single 3.3V ±5% Power Supply. 5V Tolerant Inputs except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. Asynchronous Output Enable Control. ADSP, ADSC, ADV Burst Control Pins. LBO Pin allows a choice of either a interleaved burst or a linear burst. · Three Chip Enables for simple depth expansion with No Data Contention. · TTL-Level Three-State Output. · 100-TQFP-1420A · · · · · · · · · · · ·
64Kx36 Synchronous SRAM
GENERAL DESCRIPTION
The KM736V687 is 2,359,296 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 64K words of 36 bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The KM736V687 is implemented with SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol t CYC tCD tOE -8 12 8.5 4 -9 12 9 4 -10 Unit 15 10 5 ns ns ns
LOGIC BLOCK DIAGRAM
CLK LBO CO NT RO L REGISTER ADV ADSC BURST CONTROL LOGIC BURST ADDRESS COUNTER A0~A1
64Kx36 MEMORY ARRAY
A0~A1 ADDRESS REGISTER A2~A15
ADSP
A0~A15
CS1 CS2 CS2 GW BW WEa WEb WEc WEd OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd
DATA-IN REGISTER CO NT RO L REGISTER
CONTROL LOGIC
OUTPUT BUFFER
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May 1997 Rev 1.0
PRELIMINARY
KM736V687
PIN CONFIGURATION(TOP VIEW)
ADSC ADSP WEd WEb WEa WEc A DV 83 CLK CS 1 CS 2 CS 2 VDD GW VSS BW OE A6 A7 A8 82 A9 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
64Kx36 Synchronous SRAM
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VSS
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
LBO
N.C.
N.C.
N.C.
N.C.
A15
PIN NAME
SYMBOL A0 - A15 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49, 81,82,99,100 83 84 85 89 98 97 92 93,94,95,96 86 88 87 64 31 SYMBOL VDD VSS N.C. D Q a 0~ a 7 D Q b 0~ b 7 D Q c 0~c 7 D Q d 0~ d 7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,42,43,50,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV ADSP ADSC CLK CS1 CS2 CS2 WE x OE GW BW ZZ LBO
Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
Output Power Supply (+3.3V) Output Ground
N.C.
50
DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
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May 1997 Rev 1.0
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