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Details, datasheet, quote on part number:KM736V747T
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| Part: | KM736V747T |
| Category: | Memory => SRAM => Sync. SRAM => 4 Mb => NtRAM(FT & PP) |
| Description: | Description = KM736V747T 128Kx36 Flow-through NtRAM™ ;; Organization = 128Kx36 ;; Operating Mode = FT(SB) ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 8.0,9.0,10.0 ;; Speed-tcyc (MHz) = 100,83,83 ;; I/o Voltage(V) = 2.5,3.3 ;; Package = 100TQFP ;; Production Status = Eol ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KM736V747T datasheet File size : 394 kB |
| Request For quote: | Find where to buy KM736V747T
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Datasheet text preview:
KM736V747 KM718V847
Document Title
128Kx36 & 256Kx18 Flow-Through NtRAMTM
128Kx36 & 256Kx18-Bit Flow Through NtRAMTM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed tCD from 8.0ns to 8.5ns at -8 2. Changed tCYC from 13ns to 12ns at -10 3. Changed DC condition at Icc and parameters ISB1 ; from 10mA to 30mA, ISB2 ; from 10mA to 30mA Add VDDQ Supply voltage( 2.5V I/O ) Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O. Final spec Release Remove VDDQ Supply voltage(2.5V I/O) Add VDDQ Supply voltage(2.5V I/O) Change tCD value form 8.5ns to 8.0ns at -8 Draft Date July. 15. 1998 Oct. 10. 1998 Remark Preliminary Preliminary
0.2 0.3 1.0 2.0 3.0 4.0
Dec. 10. 1998 Dec. 23. 1998 Jan. 29. 1999 Feb. 25. 1999 May. 13. 1999 July. 16. 1999
Preliminary Preliminary Final Final Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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July 1999 Rev 4.0
KM736V747 KM718V847
128Kx36 & 256Kx18 Flow-Through NtRAMTM
128Kx36 & 256Kx18-Bit Flow-Through NtRAMTM
FEATURES
· 3.3V+0.165V/-0.165V Power Supply. · I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O · Byte Writable Function. · Enable clock and suspend operation. · Single READ/WRITE control pin. · Self-Timed Write Cycle. · Three Chip Enable for simple depth expansion with no data contention · A interleaved burst or a linear burst mode. · Asynchronous output enable control. · Power Down mode. · TTL-Level Three-State Outputs. · 100-TQFP-1420A Package.
GENERAL DESCRIPTION
The KM736V747 and KM718V847 are 4,718,592-bit Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The KM736V747 and KM718V847 are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -8
10 8.0 3.5
-9
12
- 1 0 Unit
12
ns ns ns
9.0 10.0 3.5 3.5
LOGIC BLOCK DIAGRAM
LBO A [0:16]or A [0:17] ADDRESS REGISTER A2~A16 or A2~A17 A0~A1 BURST ADDRESS COUNTER A0~A1 128Kx36 , 256Kx18 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER K DATA-IN REGISTER
CONTROL LOGIC
CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d or a,b) OE ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd
CONTROL REGISTER
CONTROL LOGIC BUFFER
36 or 18
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung, and its architecture and functionalities are supported by NEC and Toshiba.
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July 1999 Rev 4.0
KM736V747 KM718V847
PIN CONFIGURATION(TOP VIEW)
BWd
128Kx36 & 256Kx18 Flow-Through NtRAMTM
BWb
BWa
BWc
CKE
ADV
N.C.
N.C. 83
CL K
CS1
CS2
CS2
VDD
VSS
WE
OE
A6
A7
A8 82
100
99
98
97
95
94
93
92
91
90
89
88
87
86
85
84
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
PIN NAME
SYMBOL A0 - A16 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL VDD VSS N.C. DQa0 ~ a 7 DQb0 ~ b 7 DQc0~c7 DQd0 ~ d 7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,16,41,65,91 14,17,40,66,67,90 38,39,42,43,83,84 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV WE CLK CKE CS1 CS2 CS2 B W x(x=a,b,c,d) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
LBO
VSS
Output Power Supply (2.5V or 3.3V) Output Ground
Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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A16
50
DQPc DQc0 DQc1 VDDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ VDDQ DQc6 DQc7 Vss VDD VDD VSS DQd0 DQd1 VDDQ V SSQ DQd2 DQd3 DQd4 DQd5 V SSQ VDDQ DQd6 DQd7 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
KM736V747(128Kx36)
DQPb DQb7 DQb6 V DDQ V SSQ DQb5 DQb4 DQb3 DQb2 V SSQ V DDQ DQb1 DQb0 V SS V SS VDD ZZ DQa7 DQa6 V DDQ V SSQ DQa5 DQa4 DQa3 DQa2 V SSQ V DDQ DQa1 DQa0 DQPa
96
July 1999 Rev 4.0
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