|
Details, datasheet, quote on part number:KMM364C213CK
| |
| Part: | KMM364C213CK |
| Category: | Memory => DRAM => Async DRAM => Modules => Buffered DIMM |
| Description: | Description = KMM364C213CK 2Mx64 DRAM Dimm Using 2Mx8,2K Refresh,5V ;; Density(MB) = - ;; Organization = 2Mx64 ;; Mode = Fast Page ;; Refresh = 2K/32ms ;; Speed(ns) = 50,60 ;; #of Pin = 168 ;; Component Composition = (2Mx8)x8+Drive ICx2 ;; Production Status = Eol ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KMM364C213CK datasheet File size : 466 kB |
| Request For quote: | Find where to buy KMM364C213CK
|
| |
Datasheet text preview:
DRAM MODULE
KMM364E213CK/CS EDO Mode 2M x 64 DRAM DIMM using 2Mx8, 2K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM364E213C is a 2Mx64bits Dynamic RAM high density memory module. The Samsung KMM364E213C consists of eight CMOS 2Mx8bits DRAMs in SOJ/TSOP-II 300mil package, and two 16bits driver IC in 48pin TSSOP package mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM364E213C is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets.
KMM364E213CK/CS
FEATURES
· Part Identification - KMM364E213CK (2048 cycles/32ms Ref., SOJ) - KMM364E213CS (2048 cycles/32ms Ref., TSOP) · Extended Data Out Mode Operation · CAS-before-RAS Refresh capability · RAS-only and Hidden refresh capability · TTL compatible inputs and outputs · Single 5V±10% power supply · JEDEC standard pinout & Buffered PDpin · Buffered input except RAS and DQ
PERFORMANCE RANGE
Speed -5 -6
tRAC
50ns 60ns
tCAC
18ns 20ns
tRC
84ns 104ns
tHPC
20ns 25ns
· PCB : Height(1000mil), single sided component
PIN CONFIGURATIONS
Pin Front Pin Front Pin Front Pin 1 VSS 2 DQ0 3 DQ1 4 DQ2 5 DQ3 6 VCC 7 DQ4 8 DQ5 9 DQ6 10 DQ7 1 1 *DQ8 12 VSS 13 DQ9 14 DQ10 15 DQ11 16 DQ12 17 DQ13 18 VCC 19 DQ14 20 DQ15 21 DQ16 22 *DQ17 23 VSS 24 RSVD 25 RSVD 26 VCC 27 W0 28 CAS0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 CAS2 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 *A12 VCC RFU RFU VSS OE2 RAS2 CAS4 CAS6 W2 VCC RSVD RSVD DQ18 DQ19 VSS DQ20 DQ21 Back Pin Back Pin Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 *DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 *DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC 57 DQ22 85 VSS 113 CAS3 58 DQ23 86 DQ36 114 *RAS1 59 VCC 87 DQ37 115 RFU 60 DQ24 88 DQ38 116 VSS 61 RFU 89 DQ39 117 A1 62 RFU 90 A3 VCC 118 63 RFU 91 DQ40 119 A5 64 RFU 92 DQ41 120 A7 65 DQ25 93 DQ42 121 A9 66 *DQ26 94 DQ43 122 *A11 67 DQ27 95 *DQ44 123 *A13 68 VSS 96 VSS 124 VCC 69 DQ28 97 DQ45 125 RFU 70 DQ29 98 DQ46 126 B0 71 DQ30 99 DQ47 127 VSS 72 DQ31 100 DQ48 128 RFU 73 VCC 101 DQ49 129 *RAS3 74 DQ32 102 VCC 130 CAS5 75 DQ33 103 DQ50 131 CAS7 76 DQ34 104 DQ51 132 PDE 77 *DQ35 105 DQ52 133 VCC 78 VSS 106 *DQ53 134 RSVD 79 PD1 107 VSS 135 RSVD 80 PD3 108 RSVD 136 DQ54 81 PD5 109 RSVD 137 DQ55 82 PD7 110 VCC 138 VSS 83 ID0 111 RFU 139 DQ56 84 VCC 112 CAS1 140 DQ57
PIN NAMES
Pin Names A0, B0, A1 - A10 DQ0 - DQ71 W0, W2 OE, OE2 RAS0, RAS2 CAS0 ~ CAS7 VCC VSS NC PDE PD1 - 8 ID0 - 1 RSVD RFU Function Address Input (2K ref.) Data In/Out Read/Write Enable Output Enable Row Address Strobe Column Address Strobe Power(+5V) Ground No Connection Presence Detect Enable Presence Detect ID bit Reserved Use Reserved for Future Use
Pins marked * are not used in this module.
PD & ID Table
Pin PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 50NS 1 0 0 1 1 0 0 1 0 0 60NS 1 0 0 1 1 1 1 1 0 0
PD Note : PD & ID Terminals must each be pulled up through a register to V CC at the next higher level assembly. PDs will be either open (NC) or driven to V SS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to V SS without a buffer. ID : 0 for Vss & 1 for N.C
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0 CAS0 W0 OE0 A0 A1-A10 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CAS1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 CAS2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 CAS3 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7 RAS2 CAS4 W2 OE2 B0 A1-A10 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 CAS5 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 CAS6 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ62 DQ61 CAS7 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70
KMM364E213CK/CS
U0
DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7
U4
U1
DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7
U5
U2
DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7
U6
U3
DQ0 DQ1 DQ2 DQ3 DQ4 DD5 DQ6 DQ7
U7
Vcc Vss
0.1 or 0.22uF Capacitor under each DRAM
To all DRAMs
A0 B0 A1-An W0, 2 OE0, 2
U0-U3 U4-U7 A1-An : U0-U7
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS
KMM364E213CK/CS
Rating -1 to +7.0 -1 to +7.0 -55 to +125 8 50 Unit V V °C W mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item Supply Voltage Ground Input High Voltage Input Low Voltage *1 : VCC+2.0V/20ns, Pulse width is measured at VCC. *2 : -2.0V/20ns, Pulse width is measured at VSS. Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0
*2
Typ 5.0 0 -
Max 5.5 0 VCC+1*1 0.8
Unit V V V V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM364E213CK/CS Min
-
Max 880 800 100 880 800 720 640 30 880 800 40 10 0.4
Unit mA mA mA mA mA mA mA mA mA mA uA uA V V
-40 -10 2.4 -
ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : EDO Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) II(L) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) IO(L) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one hyper page mode cycle, tHPC.
|
|
