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Details, datasheet, quote on part number:KMM368L6423AT-GZ
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| Part: | KMM368L6423AT-GZ |
| Category: | Memory => DRAM => DDR SDRAM => Modules => Unbuffered DIMM |
| Description: | Description = KMM368L6423AT 64Mx64 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 512 ;; Organization = 64Mx64 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; #of Pin = 184 ;; Power = C,l ;; Component Composition = (32Mx8)x16 ;; Production Status = Eol ;; Comments = Non Ecc |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KMM368L6423AT-GZ datasheet File size : 157 kB |
| Request For quote: | Find where to buy KMM368L6423AT-GZ
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Datasheet text preview:
KMM368L6423AT
Preliminary 184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx64(32Mx64*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
Revision 0.0 Sep. 1999
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Rev. 0.0 Sep. 1999
KMM368L6423AT
Revision History
Revision 0 (Sep 1999)
1. First release for internal usage
Preliminary 184pin Unbuffered DDR SDRAM MODULE
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Rev. 0.0 Sep. 1999
KMM368L6423AT
Preliminary 184pin Unbuffered DDR SDRAM MODULE
KMM368L6423AT DDR SDRAM 184pin DIMM
64Mx64 DDR SDRAM 184pin DIMM based on 32Mx8 1. GENERAL DESCRIPTION
The Samsung KMM368L6423AT is 32M bit x 64 Double Data Rate SDRAM high density memory module based on first gen. of 256Mb DDR SDRAM respectively. The Samsung KMM368L6423AT consists of sixteen CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The KMM368L6423AT Dual In-line Memory Module and is intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
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2. FEATURE
· Performance range
Part No. KMM368L6423AT-G(F)Z KMM368L6423AT-G(F)Y KMM368L6423AT-G(F)0 Max Freq. 133MHz(7.5ns@CL=2) 133MHz(7.5ns@CL=2.5) 100MHz(10ns@CL=2) SSTL_2 Interface
· Power supply Vdd: 2.5V ± 0.2V Power: G - normal, F - Low power · MRS cycle with address key programs CAS Latency (Access from column address):2,2.5 Burst length ;2, 4, 8 Data scramble ;Sequential & Interleave · Serial presence detect with EEPROM · PCB : Height 1450 (mil), double sided component
3. PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK0 /CK0 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 A5 33 DQ24 34 VSS 35 DQ25 36 DQS3 37 A4 38 VDD 39 DQ26 40 DQ27 41 A2 42 VSS 43 A1 44 *CB0 45 *CB1 46 VDD 47 *DQS8 48 A0 49 *CB2 50 VSS 51 *CB3 52 BA1 KEY 53 DQ32 54 VDDQ 55 DQ33 56 DQS4 57 DQ34 58 VSS 59 BA0 60 DQ35 61 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK1 /CK1 VSS *DM8 A10 *CB6 VDDQ *CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back /RAS DQ45 VDDQ CS0 CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 V33
4. PIN DESCRIPTION
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS7 CKE0,CKE1 CS0, CS1 RAS CAS WE DM0 ~ 7 VDD VDDQ VSS VREF V33 SDA SCL SA0 ~ 2 WP VDDID DU Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock enable input Chip select input Row address strobe Column address strobe Write enable Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Supply (3.3V) Serial data I/O Serial clock Address in EEPROM Write protection VDD identification flag Dont use
CK0,CK0 ~ CK2, CK2 Clock input
NC No connection * These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
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Rev. 0.0 Sep. 1999
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