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Details, datasheet, quote on part number:KMM377S1620CTH
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| Part: | KMM377S1620CTH |
| Category: | Memory => DRAM => SDR SDRAM => Modules => Registered DIMM |
| Description: | Description = KMM377S1620CTH 16Mx72 Sdram Dimm With PLL & Register Based on 16Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = G8,GH,GL ;; #of Pin = 168 ;; Power = G ;; Component Composition = (16Mx4)x18+Drive ICx3+PLL+EEPROM ;; Production Status = Eol ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KMM377S1620CTH datasheet File size : 259 kB |
| Request For quote: | Find where to buy KMM377S1620CTH
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Datasheet text preview:
SDRAM MODULE
KMM377S1620CTH SDRAM DIMM (Intel 1.0 ver. Base)
KMM377S1620CTH
16Mx72 SDRAM DIMM with PLL & Register based on 16Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM377S1620CTH is a 16M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM377S1620CTH consists of eighteen CMOS 16Mx4 bit Synchronous DRAMs in TSOP-II 400mil packages, three 18-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package for clock and one 2K EEPROM in 8-pin TSSOP package for Serial Presence Detect on a 168-pin glass-epoxy substrate. One 0.22uF and two 0.0022uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM377S1620CTH is a Dual In-line Memory Module and is intented for mounting into 168pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
·Performance range Part No. KMM377S1620CTH-G8 KMM377S1620CTH-GH KMM377S1620CTH-GL Max Freq. (Speed) 125MHz (8ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
· Burst mode operation · Auto & self refresh capability (4096 Cycles/64ms) · LVTTL compatible inputs and outputs · Single 3.3V ± 0.3V power supply · MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock · Serial presence detect with EEPROM · PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VD D DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VD D DQ14 DQ15 CB0 CB1 VSS NC NC VD D WE DQM0 Pin Front Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VD D DQ20 NC *V R E F *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VD D DQ28 DQ29 DQ30 DQ31 VSS *CLK2 NC WP **SDA **SCL VD D Pin Back Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 *CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VD D *CLK1 *A12 VSS CKE0 *CS3 DQM6 DQM7 *A13 VD D NC NC CB6 CB7 VSS DQ48 DQ49 Pin Back 29 D Q M 1 CS0 30 31 DU 32 VSS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10/AP 39 BA1 40 VD D 41 VD D 42 C L K 0 43 VSS 44 DU 45 CS2 46 D Q M 2 47 D Q M 3 48 DU 49 VD D 50 NC 51 NC 52 CB2 53 CB3 54 VSS 55 DQ16 56 DQ17 VSS 85 86 DQ32 87 DQ33 88 DQ34 89 DQ35 VD D 90 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 VSS 96 97 DQ41 98 DQ42 99 DQ43 100 D Q 4 4 101 D Q 4 5 102 V D D 103 D Q 4 6 104 D Q 4 7 105 C B 4 106 C B 5 VSS 107 NC 108 NC 109 110 V D D 111 C A S 112 D Q M 4 141 D Q 5 0 142 D Q 5 1 143 V D D 144 D Q 5 2 NC 145 146 * V R E F 147 R E G E 148 V S S 149 D Q 5 3 150 D Q 5 4 151 D Q 5 5 152 V S S 153 D Q 5 6 154 D Q 5 7 155 D Q 5 8 156 D Q 5 9 157 V D D 158 D Q 6 0 159 D Q 6 1 160 D Q 6 2 161 D Q 6 3 162 V S S 163 * C L K 3 NC 164 165 * * S A 0 166 * * S A 1 167 * * S A 2 168 V D D
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 CKE0 CS0, CS2 RAS CAS WE DQM0 ~ 7 VDD VSS *VR E F REGE SDA SCL SA0 ~ 2 DU NC WP Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection Write protection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 0 Feb. 1999
SDRAM MODULE
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function
KMM377S1620CTH
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched. If CLK is held at a high or low logic level, the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VCC through 10K ohm Register on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. WP pin is connected to VSS through 47K Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask
REGE
Register enable
DQ0 ~ 63 CB0 ~ 7 WP VDD/VSS
Data input/output Check bit Write protection Power supply/ground
REV. 0 Feb. 1999
SDRAM MODULE
FUNCTIONAL FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 B0CKE0 B0A0~B0A11,BBA0,BBA1,BRAS,BCAS,BWE BDQM0 DQ0~3 10 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 10 PCLK1 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 10 PCLK3 BCS2 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 10 PCLK5 CLK CS CKE Add,CTL DQM DQ0~3
KMM377S1620CTH
D0
B1CKE0 BDQM4 DQ32~35 10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9
D1
10 DQ36~39
D10
DQ4~7
D2
BDQM5 DQ40~43 10
D11
BDQM1 DQ8~11 10 PCLK2
D3
10 DQ44~47
D12
DQ12~15 10
D4
10 CB4~7
D13
CB0~3
D5
DQ48~51 10
D14
DQ48~51 10 PCLK4
D6
BDQM6 DQ52~55 10
BDQM2 DQ20~23 10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D15
D7
DQ56~59 10
D16
DQ24~27
D8
BDQM7 DQ60~63 10 VSS
BDQM3 DQ28~31 10
CLK CS CKE Add,CTL DQM DQ0~3
D17
Vcc A0~A11,BA0~1 RAS,CAS,WE SN74ALVC162835 B0A0~B0A10,BBA0~1 BRAS,BCAS,BWE 10 CLK0 PCLK6 10k 2.7pF OE CLK FIBIN 2G AGND 1G AVCL
IY0 IY1 IY2 IY3 IY4 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6
CDC2509C REGE LE
2Y0 2Y1
FBOUT
Vcc CS0 CS2 CKE0 DQM0~7 LE OE SN74ALVC162835 BCS0 BCS2 B0CKE0 B1CKE0 BDQM0~7
Serial PD SCL WP 47K A0 A1 A2 SDA
S A 0 S A 1 SA2
REV. 0 Feb. 1999
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