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Details, datasheet, quote on part number:KMM377S1723T1
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| Part: | KMM377S1723T1 |
| Category: | Memory => DRAM => SDR SDRAM => Modules => Registered DIMM |
| Description: | Description = KMM377S1723T1 16Mx72 Sdram Dimm With PLL & Register Based on 16Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 128 ;; Organization = 16Mx72 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = G8,GH,GL ;; #of Pin = 144 ;; Power = G ;; Component Composition = (16Mx8)x9+Drive ICx2+EEPROM ;; Production Status = Eol ;; Comments = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KMM377S1723T1 datasheet File size : 187 kB |
| Request For quote: | Find where to buy KMM377S1723T1
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Datasheet text preview:
SDRAM MODULE
Revision History
Revision 3 (May 1998) - CLK Input Cap. is added by PLL Input Cap. (24pF) Revision 4 (July 1998) - "REGE" description is changed.
Preliminary KMM377S1723T1
REV. 4 July 1998
SDRAM MODULE
KMM377S1723T1 SDRAM DIMM (Intel 1.0 ver. Base)
Preliminary KMM377S1723T1
16Mx72 SDRAM DIMM with PLL & Register based on 16Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM377S1723T1 is a 16M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM377S1723T1 consists of nine CMOS 16Mx8 bit Synchronous DRAMs in TSOP-II 400mil packages, two 18-bits Drive ICs for input control signal and one 2K EEPROM in 8-pin TSSOP package for Serial Presence Detect on a 168pin glassepoxy substrate. One 0.22uF and two 0.0022uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM377S1723T1 is a Dual In-line Memory Module and is intented for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
· Performance range Part No. KMM377S1723T1-G8 KMM377S1723T1-GH KMM377S1723T1-GL · · · · · Max Freq. (Speed) 125MHz (8ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock · Serial presence detect with EEPROM · PCB : Height (1,500mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 V DD DQ14 DQ15 CB0 CB1 VSS NC NC V DD WE DQM0 Front Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front Pin DQ18 DQ19 V DD DQ20 NC *V REF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 V DD DQ28 DQ29 DQ30 DQ31 VSS *CLK2 NC WP **SDA **SCL V DD Back Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 *CS1 RAS V SS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 *A12 V SS CKE0 *CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 V SS DQ48 DQ49 Pin Back 29 DQM1 CS0 30 31 DU 32 V SS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10/AP 39 BA1 40 VDD 41 VDD 42 CLK0 43 V SS 44 DU 45 CS2 46 DQM2 47 DQM3 48 DU 49 VDD 50 NC 51 NC 52 CB2 53 CB3 54 V SS 55 DQ16 56 DQ17 VSS 85 86 DQ32 87 DQ33 88 DQ34 89 DQ35 V DD 90 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 VSS 96 97 DQ41 98 DQ42 99 DQ43 100 DQ44 101 DQ45 V DD 102 103 DQ46 104 DQ47 105 CB4 106 CB5 VSS 107 NC 108 NC 109 V DD 110 111 CAS 112 DQM4 141 DQ50 142 DQ51 V DD 143 144 DQ52 NC 145 146 *V REF 147 REGE VSS 148 149 DQ53 150 DQ54 151 DQ55 VSS 152 153 DQ56 154 DQ57 155 DQ58 156 DQ59 V DD 157 158 DQ60 159 DQ61 160 DQ62 161 DQ63 VSS 162 163 *CLK3 NC 164 165 **SA0 166 **SA1 167 **SA2 V DD 168
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 CKE0 CS0 , CS2 RAS CAS WE DQM0 ~ 7 V DD V SS *V REF REGE SDA SCL SA0 ~ 2 DU NC WP Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Don t use No connection Write protection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 4 July 1998
SDRAM MODULE
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs.
Preliminary KMM377S1723T1
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with Enables row access & precharge. RAS low. CAS low.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask
Latches column addresses on the positive going edge of the CLK with Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking)
REGE
Register enable
The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to V CC through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. WP pin is connected to V SS through 47K Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. Power and ground for the input buffers and the core logic.
DQ0 ~ 63 CB0 ~ 7 WP VDD /V SS
Data input/output Check bit Write protection Power supply/ground
REV. 4 July 1998
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