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Details, datasheet, quote on part number:KMM377S2858AT3-GH
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| Part: | KMM377S2858AT3-GH |
| Category: | Memory => DRAM => SDR SDRAM => Modules => Registered DIMM |
| Description: | Description = KMM377S2858AT3 128Mx72 Sdram Dimm With PLL & Register Based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V Sdrams With SPD ;; Density(MB) = 1024 ;; Organization = 128Mx72 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 8K/64ms ;; Speed = 1H,1L ;; #of Pin = 168 ;; Power = C ;; Component Composition = (128Mx4)x18+Drive ICx3+PLL+EEPROM ;; Production Status = Eol ;; Comments = PC100 |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KMM377S2858AT3-GH datasheet File size : 236 kB |
| Request For quote: | Find where to buy KMM377S2858AT3-GH
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Datasheet text preview:
KMM377S2858AT3
Revision History
Revision 0.1 (May 27, 1999)
PC100 Registered DIMM
· Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER. · Skip ICC4 value of CL=2 in DC characteristics in datasheet. · Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER. · Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE. · Changed "Detail C" in PCB Dimension. · Symbol Change Notice
IIL IIL IOL Before Input leakage current (inputs) Input leakage current (I/O pins) Output open @ DC characteristic table ILI Io After Input leakage current Output open @ DC characteristic table
· Test Condition in DC CHARACTERISTIC Change Notice
Symbol ICC2P , ICC3P ICC2N , ICC3N ICC4 Before CKE VIL(max), tCC = 15ns CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns 2 Banks activated After CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns 4 Banks activated
Revision 0.2 (July 5, 1999)
· Added Notes @OPERATING AC PARAMETER
Notes : 5. For -H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
· Redefind feedback capacitor value to Cb, variable value @ Functional Block Diagram.
Revision 0.3 (April 29, 2000)
· - Added the description of " Staktek' stacking technology is Samsung' stacking technology of choice." s s
Rev. 0.3 Apr. 2000
KMM377S2858AT3
KMM377S2858AT3 SDRAM DIMM (Intel 1.2 ver Base)
PC100 Registered DIMM
128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM377S2858AT3 is a 128M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM377S2858AT3 consists of eighteen CMOS Stacked 128Mx4 bit Synchronous DRAMs in two TSOP-II 400mil packages, three 18-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package for clock and one 2K EEPROM in 8-pin TSSOP package for Serial Presence Detect on a 168-pin glass-epoxy substrate. Two 0.22uF and one 0.0022uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM377S2858AT3 is a Dual In-line Memory Module and is intented for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
· Performance range Part No. KMM377S2858AT3-GH KMM377S2858AT3-GL · · · · · Max Freq. (Speed) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4 , 8 & Full page) Data scramble (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock · Serial presence detect with EEPROM · PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin Front Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC *VR E F *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS *CLK2 NC WP **SDA **SCL VDD Pin Back Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS V SS A1 A3 A5 A7 A9 BA0 A11 V DD *CLK1 A12 V SS CKE0 CS3 DQM6 DQM7 *A13 V DD NC NC CB6 CB7 V SS DQ48 DQ49 Pin Back 29 D Q M 1 CS0 30 31 DU 32 V SS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A 1 0 / A P 39 BA1 40 V DD 41 V DD 42 C L K 0 43 V SS 44 DU 45 CS2 46 D Q M 2 47 D Q M 3 48 DU 49 V DD 50 NC 51 NC 52 CB2 53 CB3 54 V SS 55 D Q 1 6 56 D Q 1 7 VSS 85 86 D Q 3 2 87 D Q 3 3 88 D Q 3 4 89 D Q 3 5 V DD 90 91 D Q 3 6 92 D Q 3 7 93 D Q 3 8 94 D Q 3 9 95 D Q 4 0 VSS 96 97 D Q 4 1 98 D Q 4 2 99 D Q 4 3 1 0 0 DQ44 1 0 1 DQ45 1 0 2 V DD 1 0 3 DQ46 1 0 4 DQ47 1 0 5 CB4 1 0 6 CB5 VSS 107 NC 108 NC 109 1 1 0 V DD 1 1 1 CAS 1 1 2 DQM4 141 D Q 5 0 142 D Q 5 1 1 4 3 V DD 144 D Q 5 2 NC 145 1 4 6 *VR E F 147 REGE VSS 148 149 D Q 5 3 150 D Q 5 4 151 D Q 5 5 VSS 152 153 D Q 5 6 154 D Q 5 7 155 D Q 5 8 156 D Q 5 9 1 5 7 V DD 158 D Q 6 0 159 D Q 6 1 160 D Q 6 2 161 D Q 6 3 VSS 162 163 *CLK3 NC 164 165 **SA0 166 **SA1 167 **SA2 1 6 8 V DD
PIN NAMES
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 CKE0 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 V DD V SS *VREF REGE SDA SCL SA0 ~ 2 DU NC WP Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection Write protection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.3 Apr. 2000
KMM377S2858AT3
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC100 Registered DIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. WP pin is connected to VSS through 47K Resistor. When WP is "high", EEPROM programming will be inhibited and the entire memory will be write-protected. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask
REGE
Register enable
DQ0 ~ 63 CB0 ~ 7 WP VDD/VSS
Data input/output Check bit Write protection Power supply/ground
Rev. 0.3 Apr. 2000
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