|
|
Part: KMM466S823CT2-F0
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> SODIMM
Description: Description = KMM466S823CT2 8Mx64 Sdram Sodimm Based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 64 ;; Organization = 8Mx64 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = 10 ;; #of Pin = 144 ;; Power = L ;; Component Composition = (8Mx8)x8+EEPROM ;; Production Status = Eol ;; Comments = PC66
Company: Samsung Semiconductor, Inc.
Datasheet: Download KMM466S823CT2-F0 datasheet File size : 543 kB
Request For quote: Find where to buy KMM466S823CT2-F0
Datasheet text preview:
KMM466S823CT2
Revision History
Revision 2 (August 1998) 1. Correct DQ No. in Fuctional Block Diagram. Change DQ8 ~ DQ15 to DQ0 ~ DQ7.
Preliminary 144pin SDRAM SODIMM
REV. 2 August 1998
KMM466S823CT2
KMM466S823CT2 SDRAM SODIMM
GENERAL DESCRIPTION
The Samsung KMM466S823CT2 is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM466S823CT2 consists of eight CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM466S823CT2 is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Preliminary 144pin SDRAM SODIMM
8Mx64 SDRAM SODIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD FEATURE
· Performance range
Part No. Max Freq. (Speed)
KMM466S823CT2-F0 · · · · ·
100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock · Serial presence detect with EEPROM · PCB : Height (1,150mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin Front Pin 51 53 55 57 59 DQ14 DQ15 VSS NC NC 52 54 56 58 60 Back Pin Front DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **SDA VDD Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **SCL VDD D Q 4 6 95 D Q 4 7 97 VSS 99 NC 1 0 1 NC 1 0 3 105 107 Voltage Key 109 C L K 0 62 C K E 0 1 1 1 VDD VDD 113 64 R A S 66 C A S 1 1 5 WE 68 * C K E 1 1 1 7 C S 0 70 * A 1 2 1 1 9 * C S 1 72 * A 1 3 1 2 1 74 C L K 1 1 2 3 DU 76 VSS VSS 125 78 NC 1 2 7 NC 80 NC 1 2 9 NC 82 VDD 131 VDD D Q 1 6 84 D Q 4 8 1 3 3 D Q 1 7 86 D Q 4 9 1 3 5 D Q 1 8 88 D Q 5 0 1 3 7 D Q 1 9 90 D Q 5 1 1 3 9 92 VSS VSS 141 D Q 2 0 94 D Q 5 2 1 4 3
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK1 CKE0 CS0 RAS CAS WE DQM0 ~ 7 VDD VSS SDA SCL DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Serial data I/O Serial clock Dont use No connection
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 2 August 1998
KMM466S823CT2
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
Preliminary 144pin SDRAM SODIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~
63
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
VDD/VSS
REV. 2 August 1998
Others parts begin by km
KM-1 KM-2 KM-3 KM-4 KM-5 KM-6 KM-7 KM-8 KM-9 KM-10 KM-11 KM-12 KM-13 KM-14 KM-15 KM-16 KM-17 KM-18 KM-19 KM-20 KM-21 KM-22
|
|
|
