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Details, datasheet, quote on part number:KS0123
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Datasheet text preview:
KS0123 Data Sheet
DIGITAL VIDEO ENCODER
The KS0123 multi-standard video encoder converts CCIR 656 8-bit multiplexed digital component video into analog baseband signals. It outputs composite video (CVBS) and S-Video simultaneously at three analog output pins. The encoder implements Macrovision revision 6.0 antitaping scheme. Additionally, it contains a color subcarrier genlock to support analog/digital video splicing. The video outputs conform to either SMPTE 170M (NTSC) or CCIR 624 (PAL) standards. 44 PLCC
MULTIMEDIA VIDEO
FEATURES
· Macrovision revision 6.0 anti-taping support · 8-bit parallel CCIR 656 CbYCr input format · Synchronizes to CCIR 656 AVE time reference codes for horizontal and vertical timing generation in slave mode operation · Generates HSYN and FIELD signals in master mode operation · Programmable subcarrier frequency, SCH phase, and synchronous field display to support MPEG II picture-coding-extension · Optional subcarrier genlock to analog sc_ref referf ence · 650 kHz or 1.3 MHz chrominance bandwidth selection · Support NTSC, PAL, PAL-M and PAL-N · Switchable pedestal with gain compensation · Selectable 37 nsec YC delay pre-compensation · Video outputs meet SMPTE 170M or CCIR 624 spec
ORDERING INFO MATION R Device KS0123 Package 44 PLCC Temperature Range 0°~+70°C
· 27 MHz DAC conversion rate · Triple 10-bit DAC' for simultaneous S-video s and composite output · 2 -wire serial host interface · 8 general purpose I/O pins · JTAG test interface · Single 5 V supply with power down mode · 44-pin PLCC package
Application
· Settop Box Video Encoding · MPEG Playback · Multimedia
BLOCK DIAGRAM
PXCK Demux and Sync extract Interpolator 4:2:2/4:4:4
R-Y LPF B-Y LPF
PD[7:0]
Chroma Modulator INT
10-bit
DAC
C
10-bit
Y HSYN FIELD
Host Interface
DAC
Y
SDA SCL SA1 SA2 RESET
Video Timing Gen JTAG
Sync & Blank insert Subcarrier Synthesizer Genlock
+
10-bit
DAC D/A Ref.
CVBS Analog Interface CSync Clamp
I/O
PALID
General purpose
SC_REF
SC_FSC
TDO
TDI TMS TCK
Genlock Interface
Modified on May/04/2000
PAGE 1 OF 44
KS0123 Data Sheet
PIN ASSIGNMENT - 44 PLCC
BYPASS
MULTIMEDIA VIDEO
VDDA
CVBS 30
VSSA
39 PD5 40 PD4 41 PD3 42 PD2 43 PD1 44 VDD 1 VSS PD0 SA2 SA1 2 3 4 5
38
37
36
35
34
33
32
31
29 28 RREF 27 VREF 26 VDDA 25 PXCK
VSSA 24 VSS 23 VDD 22 RESET 21 TCK 20 TMS 19 TDI 18 TDO 17 D0/CSYN
VDD
VSS
PD6
PD7
C
KS0123
SDA 6 7 8 9 D7/PAL_ID 10 D6/SC_SYNC 11 12 13 14 D3/HSYN 15 D2/FIELD 16 D1/CLAMP
SC_REF
TYPICAL APPLICATION
The Encoder is shown in a typical settop box application.
CHANNEL DECODER
MPEG VIDEO DECODER
VSS
SCL
D5
D4
Y
ENCODER KS0123
TV Monitor
Figure 1. Typical Application
Modified on May/04/2000
PAGE 2 OF 44
KS0123 Data Sheet
PIN DESCRIPTION
Pin Name CLOCK INPUT PXCK 25 I 27 MHz clock input. TTL/CMOS. Pin # Type Description
MULTIMEDIA VIDEO
PIXEL DATA PORT PD7 - PD0 38-44, 3 I Pixel data inputs. TTL/CMOS.
GENERAL PURPOSE PORT AND OTHER SIGNALS SC_REF D7/PAL_ID 8 9 I I/O I/O I/O I/O I/O I/O I/O I/O Subcarrier reference input. TTL. General Purpose I/O Port 7 or PAL_ID input. TTL/CMOS. General Purpose I/O Port 6 or SC_SYNC input. TTL/CMOS. General Purpose I/O Port 5. TTL/CMOS. General Purpose I/O Port 4. TTL/CMOS. General Purpose I/O Port 3 or HSYN output. TTL/CMOS. General Purpose I/O Port 2 or FIELD output. TTL/CMOS. General Purpose I/O Port 1 or CLAMP output. TTL/CMOS. General Purpose I/O Port 0 or CSYN output. TTL/CMOS.
D6/SC_SYNC 10 D5 D4 D3/HSYN D2/FIELD D1/CLAMP D0/CSYN 11 12 14 15 16 17
SERIAL MICROPROCESSOR PORT SDA SCL SA1 SA2 RESET RESET 22 I Master reset input. TTL. 6 7 5 4 I/O I I I Serial data I/O. Open drain. Serial clock input. Slave address select. TTL. Slave address select. TTL.
VIDEO OUTPUTS CVBS Y C 30 32 35 O O O Composite video output. Luminance output. Chrominance output.
DAC REFERENCE AND COMPENSATION VREF BYPASS RREF 27 33 28 I/O I/O I/O Voltage reference I/O. Connect a 0.1 µF capacitor to VSSA. Compensation capacitor. Connect a 0.1 µF capacitor to VDDA. Current setting resistor.
Modified on May/04/2000
PAGE 3 OF 44
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