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Details, datasheet, quote on part number:KS57C22532
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| Part: | KS57C22532 |
| Category: | Microcontrollers => 4 bit => S3C7(KS57) Series |
| Description: | Description = ;; ROM(KB) = - ;; RAM Nibble = - ;; I/o Pins = - ;; Interrupt (Int/Ext) = - ;; Timer/counters = - ;; Sio = - ;; LCD (Seg/Com) = - ;; ADC (BitxCh) = - ;; PWM(BitxCh) = - ;; Max. OSC.Freq. (MHz) = - ;; VDD(V) = - ;; Other Features = - ;; Package = - ;; Production Status = - |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download KS57C22532 datasheet File size : 213 kB |
| Request For quote: | Find where to buy KS57C22532
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Datasheet text preview:
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
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PRODUCT OVERVIEW
OVERVIEW
The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-1280-dot LCD direct drive capability, segment expandable circuit, 8-bit and 16-bit timer/counter, and serial I/O, the KS57C21116/C21124/C21132 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 51 pins of the 128-pin QFP package can be dedicated to I/O. Nine vectored interrupts provide fast response to internal and external events. In addition, the KS57C21116/C21124/C21132's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
The KS57C21116/C21124/C21132 microcontroller is also available in OTP (One Time Programmable) version, KS57P21132. KS57P21132 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of masked ROM. The KS57P21132 is comparable to KS57C21116/C21124/C21132, both in function and in pin configuration except ROM size.
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PRODUCT OVERVIEW
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
FEATURES SUMMARY
Memory · 3,584 × 4-bit RAM (Excluding LCD Display RAM) 16,384/24,576/32,768 × 8-bit ROM 16-Bit Timer/Counter · · · · 51 I/O Pins · · I/O: 47 pins (32 pins are configurable as SEG pins) Input only: 4 pins · · Programmable 16-bit timer External event counter Arbitrary clock frequency output External clock signal divider Configurable as two 8-bit Timers Serial I/O interface clock generator Bit Sequential Carrier · Supports 16-bit serial data transfer in arbitrary format
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Memory-Mapped I/O Structure · Data memory bank 15
Power-Down Modes · · · Idle mode (only CPU clock stops) Stop mode (main system clock stops) Subsystem clock stop mode
LCD Controller/Driver · · · · · 80 SEG × 16 COM, 88 SEG × 8 COM Terminals Internal resistor circuit for LCD bias 16 Level LCD contrast control (software) Segment expandable circuit All dot can be switched on/off
Watch Timer · · · Time interval generation: 0.5 s, 3.9 ms at 32,768 Hz 4 frequency outputs to BUZ pin Clock source generation for LCD
Oscillation Sources · · · · · Crystal, Ceramic or RC for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 0.46 MHz Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8 or 64)
8-bit Serial I/O Interface · · · · 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source
8-bit Basic Timer · · 4 interval timer functions Watch-dog timer
Instruction Execution Times · · · 0.67, 1.33, 10.7 µs at 6 MHz 0.95, 1.91, 15.3 µs at 4.19 MHz 122 µs at 32.768 kHz
8-bit Timer/Counter · · · · Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider
Comparator · · 3 Channel mode: internal reference (4-bit resolution) 2 Channel mode: external reference
Operating Temperature Interrupts · · · Five internal vectored interrupts Four external vectored interrupts Two quasi-interrupts · 40 °C to 85 °C
Operating Voltage Range · 1.8 V to 5.5 V
Package Type · 128-pin QFP
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KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU All KS57-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. CPU REGISTERS Program Counter A 15-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not increment the PC is the 1-byte REF instruction which references instructions stored in a look-up table in the ROM. Whenever a reset operation or an interrupt occurs, bits PC13 through PC0 are set to the vector address. Stack Pointer An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in general-purpose data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logical zero. During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction is executed. The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets the first register of the stack area to data memory location 0FFH. PROGRAM MEMORY In its standard configuration, the 16,384/24,576/32,768 × 8-bit ROM is divided into four areas: -- 16-byte area for vector addresses -- 96-byte instruction reference area -- 16-byte general-purpose area (0010001FH) -- 16,256/24,448/32,640-byte area for general-purpose program memory The vector address area is used mostly during reset operations and interrupts. These 16 bytes can alternately be used as general-purpose ROM. The REF instruction references 2 x 1-byte or 2-byte instructions stored in reference area locations 0020H 007FH. REF can also reference three-byte instructions such as JP or CALL. So that a REF instruction can reference these instructions, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in the REF instruction look-up area can be allocated to general-purpose use.
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