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Part: KS57C2801
Category:
Microcontrollers
-> 4 bit
-> S3C7(KS57) Series
Description: Description = KS57C2801 SAM48 Core-based 4-Bit CMOS Single-chip Microcontroller ;; ROM(KB) = - ;; RAM Nibble = - ;; I/o Pins = 14 ;; Interrupt (Int/Ext) = 1/1 ;; Timer/counters = Bt/wt ;; Sio = - ;; LCD (Seg/Com) = 16/4 ;; ADC (BitxCh) = - ;; PWM(BitxCh) = - ;; Max. OSC.Freq. (MHz) = 1MHz ;; VDD(V) = 5.5 ;; Other Features = - ;; Package = 32SOP ;; Production Status = Mass Production
Company: Samsung Semiconductor, Inc.
Datasheet: Download KS57C2801 datasheet File size : 256 kB
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Datasheet text preview:
S3C7281
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C7281 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It is built around the SAM48 core CPU and contains ROM, RAM. 14 I/O lines, buzzer and inverted buzzer output, and LCD driver/controller with an up-to-64-dot. The S3C7281 can be used for dedicated control functions in a variety of applications, and is especially designed for LCD general purpose.
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PRODUCT OVERVIEW
S3C7281
FEATURES
Memory
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Memory Mapped I/O Structure
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1024 x 8 bit program memory 64 x 4 bit data memory (Including stack and excluding LCD RAM)
Data memory bank 15
Power-Down Modes
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Idle: only CPU clock stops Stop: Main System clock and CPU clock stops Subsystem clock stop mode
14 I/O Pins
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I/O: 6 pins Output: 8 pins(Sharing with segment outputs)
Oscillation Sources 8-Bit Basic Timer
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Main: Internal RC OSC(1MHz) Sub: External 32.8kHz crystal only
4 clock source(0.26, 2.1, 8.2, 32.8ms at 1MHz) Watch-dog timer
Instruction Execution Times Watch Timer
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Main system clocks:4, 8, 64µs at 1MHz Subsystem clocks: 122 µs at 32.768 kHz
Quasi interrupt(stand by release mode only) Time divider: 3.91, 32, 125, 500ms at fw=32.8kHz BUZ, BUZ output(0.5, 1, 2, 4kHz at 1MHz, 32.8kHz)
Operating Voltage Range
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1.8 V to 5.5 V at 1MHz/32.8kHz
Key Interrupt input(Quasi-interrupt)
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Power Consumption(The LVD circuit needs 100uA or more current on all the below mode)
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Falling edge detection(KS0, KS1) Stand by mode(idle, stop) release
Main: Operation - 0.5mA at 1MHz, 3V Sub: Operation - 12µA at LCD off, 3V Idle - 5µA at LCD off idle, 3V Stop - 1µA at 5.5V
Power on RESET (Program ROM MASK option)
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Initial power on RESET Reset operation under 2.0V Operating Temperature
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- 40 °C to 85 °C
LCD Display
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16 segments and 4 common pins 2, 3, and 4 common selectable Internal resistor for LCD bias(170 K)
Package Type
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32-SOP-450A Package
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S3C7281
PRODUCT OVERVIEW
BLOCK DIAGRAM
RESET
XTIN
XTOUT
P0.3 P0.2/BUZ P0.1/BUZ P0.0/CLO
I/O Port 0
Interrupt Control Block
Sub Clock Main Clock (Internal RC OSC) Instruction Register
Basic Timer
Watchdog Timer
P1.1/KS1 I/O Port 1 P1.0/KS0
Internal Interrupts Instruction Decoder Arithmetic and Logic Unit
Output Port 2
Program Counter
Watch Timer COM0-COM1
Program Status Word
LCD Driver/ Controller
COM2-COM3/ SEG0-SEG1 SEG2-SEG9 SEG10-SEG17/ P2.7-P2.0
P2.4-P2.7/ SEG13-SEG10 P2.0-P2.3/ SEG17-SEG14
Stack Pointer Power on
RESET
* AGP Option 64 x 4-Bit Data Memory 1024-Byte Program Memory
Figure 1-1. S3C7281 Simplified Block Diagram
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Others parts begin by ks
KS-1 KS-2 KS-3 KS-4 KS-5 KS-6 KS-7 KS-8
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