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Part: M366S0424CT0-C1H
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> Unbuffered DIMM
Description: Description = M366S0424CT0 4M X 64 Sdram Dimm Based on 4M X 16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 32 ;; Organization = 4Mx64 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = 80,1H,1L ;; #of Pin = 168 ;; Power = C ;; Component Composition = (4Mx16)x4+EEPROM ;; Production Status = Eol ;; Comments = PC100
Company: Samsung Semiconductor, Inc.
Datasheet: Download M366S0424CT0-C1H datasheet File size : 224 kB
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Datasheet text preview:
M366S0424CT0
M366S0424CT0 SDRAM DIMM
PC100 Unbuffered DIMM
4Mx64 SDRAM DIMM based on 4Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung M366S0424CT0 is a 4M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S0424CT0 consists of four CMOS 4M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M366S0424CT0 is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
· Performance range Part No. Max Freq. (Speed) M366S0424CT0-C80 125MHz (8ns @ CL=3) M366S0424CT0-C1H 100MHz (10ns @ CL=2) M366S0424CT0-C1L 100MHz (10ns @ CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,375mil) , single sided component
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PIN CONFIGURATIONS (Front side/back side)
Pin F r o n t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 V DD DQ14 DQ15 *CB0 *CB1 VSS NC NC V DD WE DQM0 Pin Front P i n Front 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 VDD DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP **SDA **SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 V DD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 V DD DQ46 DQ47 *CB4 *CB5 VSS NC NC V DD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 * CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 *A12 VSS CKE0 * CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VR E F NC V SS DQ53 DQ54 DQ55 V SS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 V SS *CLK3 NC **SA0 **SA1 **SA2 VDD 2 9 DQM1 CS0 30 31 DU 32 VSS 33 A0 34 A2 35 A4 36 A6 37 A8 3 8 A10/AP 39 BA1 40 VDD 41 VDD 4 2 CLK0 43 VSS 44 NC 45 CS2 4 6 DQM2 4 7 DQM3 48 NC 49 VDD 50 NC 51 NC 52 *CB2 53 *CB3 54 VSS 5 5 DQ16 5 6 DQ17
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0, CLK2 CKE0 CS0, CS2 RAS CAS WE DQM0 ~ 7 V DD V SS *VREF SDA SCL SA0 ~ 2 WP DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Write protection Dont use No connection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev.0.0 Jun. 1999
M366S0424CT0
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC100 Unbuffered DIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. WP pin is connected to VSS through 47K Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 WP VDD/VSS
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Write protection Power supply/ground
Rev.0.0 Jun. 1999
M366S0424CT0
FUNCTIONAL BLOCK DIAGRAM
CS0 DQM0 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 · ·
PC100 Unbuffered DIMM
DQM4 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS2 DQM2
U0
U2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
U1
U3
A0 ~ An, BA0 & 1 RAS CAS WE CKE0 10 DQn V DD Vss · · · ·
SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3
SCL
SDA A0 A1 A2 · WP 47K
S A 0 SA1 S A 2 10 CLK0/2 15p F
· ·
U0/U2 U1/U3
Every DQpin of SDRAM 10 CLK1/3 Two 0.1uF Capacitors per each SDRAM To all SDRAMs 10p F
Rev.0.0 Jun. 1999
Others parts begin by m3
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