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Part: M366S3253CTU-C1H
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> Unbuffered DIMM
Description: Description = M366S3253CTU 32M X 64 Sdram Dimm Based on 32M X 8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 256 ;; Organization = 32Mx64 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 8K/64ms ;; Speed = 7A,1H,1L ;; #of Pin = 168 ;; Power = C,l ;; Component Composition = (32Mx8)x8+EEPROM ;; Production Status = Mass Production ;; Comments = For 1U(Low Height) Server,PC100&PC66,7C:EOL
Company: Samsung Semiconductor, Inc.
Datasheet: Download M366S3253CTU-C1H datasheet File size : 224 kB
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Datasheet text preview:
M366S3253CTU
M366S3253CTU SDRAM DIMM
PC133/PC100 Low Profile Unbuffered DIMM
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung M366S3253CTU is a 32M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S3253CTU consists of eight CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM and two 2.2uF bulk capacitors per DIMM. The M366S3253CTU is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
· Performance range Part No. M366S3253CTU-L7C/C7C M366S3253CTU-L7A/C7A M366S3253CTU-L1H/C1H M366S3253CTU-L1L/C1L · · · · · Max Freq. (Speed) 133MHz (7.5ns@CL=2) 133MHz (7.5ns@CL=3) 100MHz (6.0ns@CL=2) 100MHz (6.0ns@CL=3)
Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock · Serial presence detect with EEPROM · PCB : Height (1,125mil), single sided component
PIN CONFIGURATIONS (Front side/back side)
P i n F r o n t Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 V SS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 V SS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 V SS NC NC VDD WE DQM0 Front P i n F r o n t Pin Back Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 *CS1 RAS V SS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 A12 V SS CKE0 *CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 V SS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC * V REF NC V SS DQ53 DQ54 DQ55 V SS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 V SS *CLK3 NC **SA0 **SA1 **SA2 VDD 29 D Q M 1 CS0 30 31 DU 32 VSS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A 1 0 / A P 39 BA1 40 VDD 41 VDD 42 C L K 0 43 VSS 44 DU 45 CS2 46 D Q M 2 47 D Q M 3 48 DU 49 VDD 50 NC 51 NC 52 * C B 2 53 * C B 3 54 VSS 55 D Q 1 6 56 D Q 1 7 5 7 D Q 1 8 85 VSS 5 8 D Q 1 9 86 D Q 3 2 59 87 D Q 3 3 VDD 6 0 D Q 2 0 88 D Q 3 4 61 89 D Q 3 5 NC 6 2 *VR E F 9 0 VDD 6 3 * C K E 1 91 D Q 3 6 64 92 D Q 3 7 V SS 6 5 D Q 2 1 93 D Q 3 8 6 6 D Q 2 2 94 D Q 3 9 6 7 D Q 2 3 95 D Q 4 0 68 96 VSS V SS 6 9 D Q 2 4 97 D Q 4 1 7 0 D Q 2 5 98 D Q 4 2 7 1 D Q 2 6 99 D Q 4 3 7 2 D Q 2 7 100 D Q 4 4 73 V D D 101 D Q 4 5 7 4 D Q 2 8 102 V D D 7 5 D Q 2 9 103 D Q 4 6 7 6 D Q 3 0 104 D Q 4 7 7 7 D Q 3 1 105 * C B 4 78 V S S 106 * C B 5 79 CLK2 107 VSS 80 NC 108 N C 81 * W P 109 N C 8 2 * * S D A 110 V D D 8 3 * * S C L 111 C A S 84 V D D 112 D Q M 4
PIN NAMES
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CLK0, CLK2 CKE0 CS0, CS2 RAS CAS WE DQM0 ~ 7 VDD VSS *VR E F SDA SCL SA0 ~ 2 *WP DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Write protection Dont use No connection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001
M366S3253CTU
Pin CLK CS Name System clock Chip select
PC133/PC100 Low Profile Unbuffered DIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
PIN CONFIGURATION DESCRIPTION
CKE
Clock enable
A0 ~ A12 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 VDD/VSS
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
Rev. 0.1 Sept. 2001
M366S3253CTU
FUNCTIONAL BLOCK DIAGRAM
CS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ·
PC133/PC100 Low Profile Unbuffered DIMM
DQM4 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
U0
U4
U1
· DQM6 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
U2
U6
U3
U7
Serial PD SCL 47K WP A0 SDA A1 A2
SA0 SA1 SA2
A0 ~ An, BA0 & 1 RAS CAS WE CKE0 10 DQn VDD Vss · · · ·
SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 3 . 3 pF* 1 Every DQpin of SDRAM CLK0/1 · 10 · · ·
U0/U9 U5/U14 U2/U10 U1/U15 U6/U11
*1 : For 4 loads, CLK2 & CLK3 only. 10
Two 0.1uF Capacitors per each SDRAM
To all SDRAMs
CLK2/3 1 0 pF
Rev. 0.1 Sept. 2001
Others parts begin by m3
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