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Part: M368L6423DTL
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> Unbuffered DIMM
Description: Description = M368L6423DTL 64Mx64 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 512 ;; Organization = 64Mx64 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; #of Pin = 184 ;; Power = C,l ;; Component Composition = (32Mx8)x16 ;; Production Status = Mass Production ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download M368L6423DTL datasheet File size : 224 kB
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Datasheet text preview:
M368L6423DTL
184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx64(32Mx64*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
Revision 0.2 May. 2002
Rev. 0.2 May. 2002
M368L6423DTL
Revision History
Revision 0 (Dec. 2001)
1. First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Revision 0.1 (Jan, 2002)
1. Changed to final version 2. Added tRAP(Active to Read w/ autoprecharge command)
Revision 0.2 (May, 2002)
1. Change pin location of A13 from pin 103 to pin 167
Rev. 0.2 May. 2002
M368L6423DTL
184pin Unbuffered DDR SDRAM MODULE
M368L6423DTL DDR SDRAM 184pin DIMM
64Mx64 DDR SDRAM 184pin DIMM based on 32Mx8 GENERAL DESCRIPTION
The Samsung M368L6423DTL is 32M bit x 64 Double Data Rate SDRAM high density memory module. The Samsung M368L6423DTL consists of sixteen CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M368L6423DTL Dual In-line Memory Module and is intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
· Performance range Part No. Max Freq. Interface SSTL_2 M368L6423DTL-C(L)B3 1 6 7 M H z ( 6 . 0 n s @ C L = 2 . 5 ) M368L6423DTL-C(L)A2 133MHz(7.5ns@CL=2) M368L6423DTL-C(L)B0 1 3 3 M H z ( 7 . 5 n s @ C L = 2 . 5 ) · Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
· Double-data-rate architecture; two data transfers per clock cycle
· Bidirectional data strobe(DQS) · Differential clock inputs(CK and CK) · DLL aligns DQ and DQS transition with CK transition · Programmable Read latency 2, 2.5 (clock) · Programmable Burst length (2, 4, 8) · Programmable Burst type (sequential & interleave) · Edge aligned data output, center aligned data input · Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) · Serial presence detect with EEPROM · PCB : Height 1250 mil , double sided component
PIN CONFIGURATIONS (Front side/back side)
P i n Front P i n Front P i n Front
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 A5 3 3 DQ24 34 VSS 3 5 DQ25 3 6 DQS3 37 A4 38 VDD 3 9 DQ26 4 0 DQ27 41 A2 42 VSS 43 A1 4 4 *CB0 4 5 *CB1 46 VDD 4 7 *DQS8 48 A0 4 9 *CB2 50 VSS 5 1 *CB3 52 BA1 KEY 5 3 DQ32 5 4 VDDQ 5 5 DQ33 5 6 DQS4 5 7 DQ34 58 VSS 59 BA0 6 0 DQ35 6 1 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
PIN DESCRIPTION
Pin Back P i n Name
A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS7 CKE0,CKE1 CS0, CS1 RAS CAS WE DM0 ~ 7 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID
Pin
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
Pin
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
Back
VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK0 /CK0 VSS *DM8 A10 *CB6 VDDQ *CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
Function
Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock enable input Chip select input Row address strobe Column address strobe Write enable Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VDD identification flag
154 /RAS 155 DQ45 156 V D D Q 157 /CS0 158 /CS1 159 DM5 160 VSS 161 DQ46 162 DQ47 163 */CS3 164 V D D Q 165 DQ52 166 DQ53 167 *A13 168 VDD 169 DM6 170 DQ54 171 DQ55 172 V D D Q 173 NC 174 DQ60 175 DQ61 176 VSS 177 DM7 178 DQ62 179 DQ63 180 V D D Q 181 SA0 182 SA1 183 SA2 184 VDDSPD
CK0, CK0 ~ CK2, CK2 Clock input
NC No connection * These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 May. 2002
Others parts begin by m3
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