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Part: M372F0803ET0-C
Category:
Memory
-> DRAM
-> Async DRAM
-> Modules
-> Buffered DIMM
Description: Description = M372F0803ET0 8Mx72 DRAM Dimm With Ecc Using 8Mx8,4K&8KRefresh,3.3V ;; Density(MB) = 64 ;; Organization = 8Mx72 ;; Mode = Edo ;; Refresh = 4K ;; Speed(ns) = 50,60 ;; #of Pin = 168 ;; Component Composition = (8Mx8)x9+EEPROM ;; Production Status = Eol ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download M372F0803ET0-C datasheet File size : 1492 kB
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Datasheet text preview:
DRAM MODULE
M372F080(8)3EJ(T)0-C
M372F080(8)3EJ(T)0-C EDO Mode 8M x 72 DRAM DIMM with ECC Using 8Mx8, 4K & 8K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung M372F080(8)3EJ(T)0-C is a 8Mx72bits Dynamic RAM high density memory module. The Samsung M372F080(8)3EJ(T)0-C consists of nine CMOS 8Mx8bits DRAMs in SOJ/TSOP-II 400mil packages and two 16 bits driver IC in TSSOP package mounted on a 168-pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M372F080(8)3EJ(T)-C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets.
FEATURES
· Part Identification Part number M372F0803EJ0-C M372F0803ET0-C M372F0883EJ0-C M372F0883ET0-C · · · · · · · · PKG SOJ TSOP SOJ TSOP Ref. 4K 8K CBR Ref. ROR Ref.
4K/64ms 4K/64ms 8K/64ms
PERFORMANCE RANGE
Speed -C50 -C60
tR A C
50ns 60ns
tC A C
18ns 20ns
t RC
84ns 104ns
tH P C
20ns 25ns
Extended Data Out Mode Operation CAS-before-RAS Refresh capability RAS-only and Hidden refresh capability LVTTL compatible inputs and outputs Single 3.3V±0.3V power supply JEDEC standard pinout & Buffered PDpin Buffered input except RAS and DQ PCB : Height(1250mil), single sided component
PIN CONFIGURATIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front Pin VS S DQ0 DQ1 DQ2 DQ3 VC C DQ4 DQ5 DQ6 DQ7 DQ8 VS S DQ9 DQ10 DQ11 DQ12 DQ13 VC C DQ14 DQ15 DQ16 DQ17 VS S RSVD RSVD VC C W0 CAS0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front *CAS2 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 V CC RFU RFU VSS OE2 RAS2 CAS4 *CAS6 W2 V CC RSVD RSVD DQ18 DQ19 VSS DQ20 DQ21 P i n Front 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ22 DQ23 VCC DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VS S DQ36 DQ37 DQ38 DQ39 VC C DQ40 DQ41 DQ42 DQ43 DQ44 VS S DQ45 DQ46 DQ47 DQ48 DQ49 VC C DQ50 DQ51 DQ52 DQ53 VS S RSVD RSVD VC C RFU * CAS1 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back *CAS3 *RAS1 RFU VSS A1 A3 A5 A7 A9 A11 *A13 VCC RFU B0 VSS RFU *RAS3 *CAS5 *CAS7 PDE VCC RSVD RSVD DQ54 DQ55 VSS DQ56 DQ57 P i n Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC
PIN NAMES
P i n Names A0, B0, A1 - A11 A0, B0, A1 - A12 D Q 0 - DQ71 W 0 , W2 OE0 , OE2 RAS0 , RAS2 CAS0 , CAS4 VC C VSS NC PDE PD1 - 8 ID0 - 1 RSVD RFU Function Address Input(4K ref.) Address Input(8K ref.) Data In/Out Read/Write Enable Output Enable Row Address Strobe Column Address Strobe Power(+3.3V) Ground No Connection Presence Detect Enable Presence Detect ID bit Reserved Use Reserved for Future Use
Pins marked * are not used in this module.
PD & ID Table
Pin PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0
50NS 1 0 1 1 1 0 0 0 0
60NS 1 0 1 1 1 1 1 0 0 0
NOTE : A12 is used for only M372F0883EJ0/ET0-C (8K Ref.)
ID1 0 PD Note :PD & ID Terminals must each be pulled up through a register to VCC at the next higher level assembly. PDs will be either open (NC) or driven to V S S via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer. ID : 0 for Vss & 1 for N.C
REV. 0.0 Apr. 2001
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0 CAS0 OE0 W0 A0 A1-A11(A12) DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RAS2 CAS4 OE2 W2 B0 A1-A11(A12)
M372F080(8)3EJ(T)0-C
U0
U5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
U1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
U6
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
U2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
U7
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
U3
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
U8
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71
Vcc Vss
U4
0.1 or 0.22uF Capacitor under each DRAM
To all DRAMs
NOTE : A12 is used for only M372F0883EJ0/ET0 (8K Ref.)
A0 B0 A1-A11(A12) W 0, OE0 W 2, OE2
U0-U4 U5-U8 U0-U8 U0-U4 U5-U8
REV. 0.0 Apr. 2001
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item Voltage on any pin relative V S S Voltage on V CC supply relative to V S S Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN , VOUT V CC T stg PD IO S
M372F080(8)3EJ(T)0-C
Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +125 9 50 Unit V V °C W mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VC C VSS VI H VIL Min 3.0 0 2.0 -0.3 * 2 Typ 3.3 0 Max 3.6 0 VCC + 0 . 3*1 0.8 Unit V V V V
*1 : VCC+1.3V at pulse width 15ns, which is measured at VCC . *2 : -1.3V at pulse width15ns, which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol IC C 1 IC C 2 IC C 3 IC C 4 IC C 5 IC C 6 I I(L) IO(L) VO H VOL Speed -50 -60 Don t care -50 -60 -50 -60 Don t care -50 -60 Don t care Don t care M372F0803EJ(T)0 Min
-
M372F0883EJ(T)0 Min -10 -5 2.4 Max 720 630 100 720 630 810 720 30 990 900 10 5 0.4
Max 990 900 100 990 900 810 720 30 990 900 10 5 0.4
Unit mA mA mA mA mA mA mA mA mA mA uA uA V V
-10 -5 2.4 -
ICC1* : Operating Current * ( R A S, CAS , Address cycling @tR C=min) ICC2 : Standby Current ( R A S= C A S= W = VI H) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tR C=min) ICC4* : Extended Data Out Mode Current * (RAS=V IL , CAS cycling : tHPC =min) ICC5 : Standby Current ( R A S= C A S= W =Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tR C=min) I(IL) : Input Leakage Current (Any input 0 V I NVcc+0.3V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0V VO U T Vcc) VO H : Output High Voltage Level (I O H = -2mA) VO L : Output Low Voltage Level (I OL = 2mA) * NOTE : IC C 1 , ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. IC C is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.
REV. 0.0 Apr. 2001
Others parts begin by m3
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