Details, datasheet, quote on part number: M378T6553CZ3-CD5
PartM378T6553CZ3-CD5
Category
DescriptionDDR2 Unbuffered Sdram Module 240pin Unbuffered Module Based on 512mb C-die 64/72-bit Non-ecc/ecc
CompanySamsung Semiconductor, Inc.
DatasheetDownload M378T6553CZ3-CD5 datasheet
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Features, Applications

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Part Number M391T2953CZ3-CE7/E6/D5/CC M391T2953CZ0-CE7/E6/D5/CC Density 512MB 1GB Organization 128Mx64 x72 ECC 64Mx8(K4T51083QC)*9 64Mx8(K4T51083QC)*18 Component Composition 64Mx8(K4T51083QC)*8 64Mx8(K4T51083QC)*16

Note: "Z" of Part number(11th digit) stand for Lead-free products. Note: "3" of Part number(12th digit) stand for Dummy Pad PCB products.

Features

JEDEC standard 0.1V Power Supply VDDQ 0.1V 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin 4 Banks Posted CAS Programmable CAS Latency: 4, 5 Programmable Additive Latency: and 4 Write Latency(WL) = Read Latency(RL) -1 Burst Length: , 8(Interleave/nibble sequential) Programmable Sequential / Interleave Burst Mode Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) Off-Chip Driver(OCD) Impedance Adjustment On Die Termination with selectable values(50/75/150 ohms or disable) PASR(Partial Array Self Refresh) Average Refresh Period 7.8us at lower than a TCASE 85C < TCASE C - support High Temperature Self-Refresh rate enable feature Package: 60ball FBGA , 84ball FBGA - 32Mx16 All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung's Device operation & Timing diagram.

Organization 64Mx8(512Mb) based Module 32Mx16(512Mb) based Module Row Address A0-A13 A0-A12 Column Address A0-A9 Bank Address BA0-BA1 Auto Precharge A10

= No Connect, RFU = Reserved for Future Use Pin196(A13) is used for x4/x8 base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)


 

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