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Part: M381L6523BTM-CLA2
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> Unbuffered DIMM
Description: Description = M381L6523BTM 184Pin Unbuffered Dimm Based on 512Mb B-die (x8, X16) ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,AA,A2,B0 ;; #of Pin = 184 ;; Power = C,l ;; Component Composition = (64Mx8)x9 ;; Production Status = Customer Sample ;; Comments = DDR266/333/400
Company: Samsung Semiconductor, Inc.
Datasheet: Download M381L6523BTM-CLA2 datasheet File size : 680 kB
Request For quote: Find where to buy M381L6523BTM-CLA2
Datasheet text preview:
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 512Mb B-die with 64/72-bit ECC/Non ECC
Revision 0.1 August. 2003
Rev. 1.0 August. 2003
256MB, 512MB, 1GB Unbuffered DIMM
Revision History
Revision 0.0 (February, 2003) - First release Revision 1.0 (August, 2003) - Finalized.
DDR SDRAM
Rev. 1.0 August. 2003
256MB, 512MB, 1GB Unbuffered DIMM
184Pin Unbuffered DIMM based on 512Mb B-die (x8, x16)
Ordering Information
Part Number M368L3324BTM-C(L)B3/AA/A2/B0 M368L6523BTN-C(L)B3/AA/A2/B0 M381L6523BTM-C(L)B3/AA/A2/B0 M368L2923BTN-C(L)B3/AA/A2/B0 M381L2923BTM-C(L)B3/AA/A2/B0 D ensity 256MB 512MB 512MB 1GB 1GB Organization 32M x 64 64M x 64 64M x 72 128M x 64 128M x 72
DDR SDRAM
Component Composition 32Mx16 (K4H511638B) * 4EA 64Mx8 (K4H510838B) * 8EA 64Mx8 (K4H510838B) * 9EA 64Mx8 (K4H510838B) * 16EA 64Mx8 (K4H510838B) * 18EA
Height 1,250mil 1,250mil 1,250mil 1,250mil 1,250mil
Operating Frequencies
B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2 .5-3-3 AA(DDR266@CL=2) 133MHz 133MHz 2-2-2 A2(DDR266@CL=2) 133MHz 133MHz 2 -3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3
Feature
· Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V · Double-data-rate architecture; two data transfers per clock cycle · Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) · Differential clock inputs(CK and CK) · DLL aligns DQ and DQS transition with CK transition · Programmable Read latency 2, 2.5 (clock) · Programmable Burst length (2, 4, 8) · Programmable Burst type (sequential & interleave) · Edge aligned data output, center aligned data input · Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) · Serial presence detect with EEPROM · PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided · SSTL_2 Interface
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.0 August. 2003
Others parts begin by m3
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