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Part: M381L6523MT1
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> 512 MB
Description:
Company: Samsung Semiconductor, Inc.
Datasheet: Download M381L6523MT1 datasheet File size : 680 kB
Request For quote: Find where to buy M381L6523MT1
Datasheet text preview:
M381L6523MT1
184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx72 based on 64Mx8 DDR SDRAM)
Unbuffered 184pin DIMM 72-bit ECC/Parity
Revision 0.0 September. 2001
R e v . 0.0 Sep. 2001
M381L6523MT1
Revision History
Revision 0 (Sep 2001)
1 . First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
R e v . 0.0 Sep. 2001
M381L6523MT1
184pin Unbuffered DDR SDRAM MODULE
M381L6523MT1 DDR SDRAM 184pin DIMM
64Mx72 DDR SDRAM 184pin DIMM based on 64Mx8 G ENERAL DESCRIPTION
The Samsung M381L6523MT1 is 64M bit x 72 Double Data R a t e SDRAM high density memory modules based on first g e n of 512Mb DDR SDRAM respectively.The Samsung M 3 8 1 L 6 5 2 3 M T 1 consists of nine CMOS 64M x 8 bit with 4 b a n k s Double Data Rate SDRAMs in 66pin TSOP-II(400mil) p a c k a g e s mounted on a 184pin glass-epoxy substrate. Four 0 . 1 u F decoupling capacitors are mounted on the printed circuit b o a r d in parallel for each DDR SDRAM. The M381L6523MT1 i s Dual In-line Memory Modules and intended for mounting into 1 8 4 p i n edge connector sockets. Synchronous design allows precise cycle control with the use o f system clock. Data I/O transactions are possible on both e d g e s of DQS. Range of operating frequencies, programmable l a t e n c i e s and burst lengths allow the same device to be useful f o r a variety of high bandwidth, high performance memory syst e m applications.
FEATURE
· Performance range P a r t No. M a x Freq. Interface SSTL_2 M381L6523MT1-C(L)A2 133MHz(7.5ns@CL=2) M381L6523MT1-C(L)B0 133MHz(7.5ns@CL=2.5) M381L6523MT1-C(L)A0 100MHz(10ns@CL=2) · Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
· Double-data-rate architecture; two data transfers per clock cycle
· Bidirectional data strobe(DQS) · Differential clock inputs(CK and CK) · DLL aligns DQ and DQS transition with CK transition · Programmable Read latency 2, 2.5 (clock) · Programmable Burst length (2, 4, 8) · Programmable Burst type (sequential & interleave) · Edge aligned data output, center aligned data input · Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) · Serial presence detect with EEPROM · PCB : Height 1250 (mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
P i n F r o n t Pin F r o n t P i n
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
PIN DESCRIPTION
Pin
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
F r o n t Pin
VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 *CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
Pin
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
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VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8 A10 CB6 VDDQ CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
Back
/RAS DQ45 VDDQ /CS0 */CS1 DM5 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VD D S P D
P i n Name
A0 ~ A1 2 B A 0 ~ BA1 D Q 0 ~ DQ63 C B 0 ~ CB7 D Q S 0 ~ DQS8 C K 0 , C K 0 ~ CK2, CK2 CKE0 CS0 RAS CAS WE D M 0 ~ DM8 VDD VDDQ VSS VREF V DDSPD SDA SCL SA0 ~ 2 VDDID
Function
A d d r e s s input (Multiplexed) B a n k Select Address Data input/output Check bit(Data-in/data-out) Data Strobe input/output Clock input Clock enable input Chip select input R o w address strobe C o l u m n address strobe Write enable D a t a - in mask P o w e r supply (2.5V) P o w e r Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Supply (2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM VDD identification flag
NC N o connection * These pins are not used in this module.
S A M S U N G ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
R e v . 0.0 Sep. 2001
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