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Part: M383L6423BT0-CLA0
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> Registered DIMM
Description: Description = M383L6423BT0 64Mx72 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = Z,Y,0 ;; Power = G,f ;; #of Pin = 184 ;; Component Composition = (32Mx8)x18 ;; Production Status = Eol ;; Comments = Registered,ecc
Company: Samsung Semiconductor, Inc.
Datasheet: Download M383L6423BT0-CLA0 datasheet File size : 1140 kB
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Datasheet text preview:
M383L6423BT0
184pin Registered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx72(32Mx72*2 bank) based on 32Mx8 DDR SDRAM)
Registered 184pin DIMM 72-bit ECC/Parity
Revision 0.5 April. 2000
- -1 -
Rev. 0.5 April. 2000
M383L6423BT0
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
184pin Registered DDR SDRAM MODULE
Revision 0.1 (Aug. 1999)
1. Modified binning policy From To -Z (133Mhz) -Z (133Mhz/266Mbps@CL=2) -8 (125Mhz) -Y (133Mhz/266Mbps@CL=2.5) -0 (100Mhz) -0 (100Mhz/200Mbps@CL=2) 2.Modified the following AC spec values From. -Z tAC tDQSCK tDQSQ tDS/tDH tCDLR* 1 tPRE* 1 tRPST* 1 tHZQ* 1
*1
To. -0 +/- 1ns +/- 1ns +/- 0.75ns 0.75 ns -Z +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -Y +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -0 +/- 0.8ns +/- 0.8ns +/- 0.6ns 0.6 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/-0.8ns
+/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 2.5tCK-tDQSS 1tCK +/- 0.75ns tCK/2 +/- 0.75ns tCK/2 +/- 0.75ns
2.5tCK-tDQSS 1tCK +/- 1ns tCK/2 +/- 1ns tCK/2 +/- 1ns
: Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol From tDQCK To tAC Output data access time from CK/CK .
Revision 0.2 (Sept. 1999)
1. Changed the odering information. 1-1. Exclude KM mark. From KMM381... 1-2. PCB Revison From - Blank: 1st generation -A : 2nd generation -B : 2nd generation Example:KMM383L6423AT 1-3. Modified binning policy From - 0 (100Mhz/200Mbps@CL=2) - Z (133Mhz/266Mbps@CL=2) - Y (133Mhz/266Mbps@CL=2.5)
To M381.....
To - 0: 1st gernation - 1: 2nd generation - 2: 3nd generation M383L6423AT0
To - A0 (100Mhz/200Mbps@CL=2) - A2 (133Mhz/266Mbps@CL=2) - B0 (133Mhz/266Mbps@CL=2.5)
-0-
Rev. 0.5 April. 2000
M383L6423BT0
Revision 0.3 (December. 1999)
1. Changed from 3.3V to 2.5V in VDDSPD power.
184pin Registered DDR SDRAM MODULE
Revision 0.4 (April. 2000)
1. Changed pin 90 from WP to NC in pin configuration table. 2. Removed WP in pin description. 3. Changed bypassing to reflect common Vdd/Vddq plane. 4. Added A12, BA1. 5. Removed WP from serial PD.
6. Changed Power & DC operating condition. From Min
I/O Reference voltage Input logic high voltage Input logic low voltage Input leakage current Output High Current (VOUT = 1.95V) Output Low Current (VOUT = 0.35V) V REF VIH(DC) VIL(DC) II IO H IOL 1.15 V R E F +0.18 -0.3 -5 -15.2 15.2
Parameter
Symbol
To Max
1.35
Min
0.49*VDDQ VREF+0.15 -0.3 -2 -16.8 16.8
Max
0.51*VDDQ V D D Q +0.3 VREF -0.15 2
VDDQ +0.3 VREF-0.18 5
7. Added Overshoot/Undershoot spec . Vih(max) = 4.2V, the overshoot voltage duration is 3ns at VDD. . Vil(min) =- 1.5V, the overshoot voltage duration is 3ns at VSS. 8. Changed AC operating conditions as follows. Parameter/Condition Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VREF + 0.35 VREF - 0.35 VDDQ+0.6 0.62 From Max Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 To Max
9. Changed AC parameters as follows. Parameter tDQSQ tDV from +/- 0.5(PC266), +/- 0.6(PC200) +/- 0.35tCK to +0.5(PC266), +0.6(PC200) Removed Comments
-1-
Rev. 0.5 April. 2000
Others parts begin by m3
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