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Part: M383L6423CT1
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> Registered DIMM
Description: Description = M383L6423CT1 64Mx72 DDR Sdram 184pin Dimm Based on 32Mx8 ;; Density(MB) = 512 ;; Organization = 64Mx72 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A0,A2,B0 ;; Power = C,l ;; #of Pin = 184 ;; Component Composition = (32Mx8)x18 ;; Production Status = Eol ;; Comments = Ecc
Company: Samsung Semiconductor, Inc.
Datasheet: Download M383L6423CT1 datasheet File size : 1140 kB
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Datasheet text preview:
M383L6423CT1
184pin Registered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx72(32Mx72*2 bank) based on 32Mx8 DDR SDRAM)
Registered 184pin DIMM 72-bit ECC/Parity
Revision 0.3 May. 2002
Rev. 0.3 May. 2002
M383L6423CT1
Revision History
Revision 0 (Aug 2001)
1. First release for internal usage
184pin Registered DDR SDRAM MODULE
Revision 0.1 (Dec. 2001)
- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 47. - Revised "Absolute maximum rating" table in page 38. . Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V . Changed "power dissipation" value from 1.0W to 1.5W. - Revised AC parameter table
From DDR266A Min. tHZ tLZ tWPST (tCK) tPDEX tACmin -400ps tACmin -400ps 0.25 10ns Max. tACmax -400ps tACmax -400ps DDR266B Min. tACmin -400ps tACmin -400ps 0.25 10ns Max. tACmax -400ps tACmax -400ps DDR200 Min. tACmin -400ps tACmin -400ps 0.25 10ns Max. tACmax -400ps tACmax -400ps DDR266A Min. -0.75 -0.75 0.4 7.5ns Max. +0.75 +0.75 0.6
To DDR266B Min. -0.75 -0.75 0.4 7.5ns Max. +0.75 +0.75 0.6 DDR200 Min. -0.8 -0.8 0.4 10ns Max. +0.8 +0.8 0.6
- Deleted typical current in IDD spec. table - Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification - Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification - Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266 - Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266 - Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266 - Rename tREF(Refresh interval time) to tREFI at DDR200/266 - Changed tWR value from 2tCK to 15ns. --Rename tCDLR(Write data out to Read command) t0 tWTR - Added tDAL(tWR+tRP)
Revision 0.2 (Jan. 2002)
1.Added tRAP(Active to Read with auto precharge delay).
Revision 0.3 (May. 2002)
1 . Change pin location of A13 from pin 103 to pin 167
Rev. 0.3 May. 2002
M383L6423CT1
184pin Registered DDR SDRAM MODULE
M383L6423CT1 DDR SDRAM 184pin DIMM
64Mx72 DDR SDRAM 184pin DIMM based on 32Mx8 GENERAL DESCRIPTION
The Samsung M383L6423CT1 is 64M bit x 72 Double Data Rate SDRAM high density memory modules. The Samsung M383L6423CT1 consists of eighteen CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages, mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M383L6423CT1 is Dual In-line Memory Modules and intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
· Performance range Part No. Max Freq. Interface SSTL_2 M383L6423CT1-C(L)A2 1 3 3 M H z ( 7 . 5 n s @ C L = 2 ) M383L6423CT1-C(L)B0 133MHz(7.5ns@CL=2.5) M383L6423CT1-C(L)A0 100MHz(10ns@CL=2) · Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
· Double-data-rate architecture; two data transfers per clock cycle
· Bidirectional data strobe(DQS) · Differential clock inputs(CK and CK) · DLL aligns DQ and DQS transition with CK transition · Programmable Read latency 2, 2.5 (clock) · Programmable Burst length (2, 4, 8) · Programmable Burst type (sequential & interleave) · Edge aligned data output, center aligned data input · Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) · Serial presence detect with EEPROM · PCB : Height 1700 mil , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Front Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 */CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
PIN DESCRIPTION
Pin
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Front
VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS */CK2 *CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
Pin
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
Pin
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
Back
VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8 A10 CB6 VDDQ CB7
Back
/RAS DQ45 VDDQ /CS0 /CS1 DM5 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Pin Name
A 0 ~ A12 BA0 ~ BA1 D Q 0 ~ DQ63 CB0 ~ CB7 D Q S 0 ~ DQS8 CK0, CK0 CKE0,CKE1 CS0, CS1 RAS CAS WE DM0 ~ DM8 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID RESET NC
Function
A d d r e s s input (Multiplexed) Bank Select Address Data input/output Check bit(Data-in/data-out) Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe C o l u m n address strobe W r i t e enable D a t a - in mask P o w e r supply (2.5V) Power Supply for DQS(2.5V) Ground P o w e r supply for reference Serial EEPROM Power Supply ( 2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM VDD identification flag Reset enable No connection
KEY
DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
KEY
VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.3 May. 2002
Others parts begin by m3
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