The Samsung a 32M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S3323BN0 consists of sixteen CMOS x 8 bit with 4banks Synchronous DRAMs in sTSOP2 package and a 2K EEPROM in 8-pin TSSOP package a 144-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length Full page) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,250mil), double sided component

Pin Front Pin VSS DQ2 DQ3 VDD DQ6 DQ7 VSS DQM0 DQM1 VDD A1 A2 VSS DQ10 DQ11 VDD DQ12 DQ13 Back VSS DQ34 DQ35 VDD DQ38 DQ39 VSS DQM4 DQM5 VDD A4 A5 VSS DQ42 DQ43 VDD DQ44 DQ45 Pin Front DQ14 DQ15 VSS NC Pin Back Pin Front DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ26 DQ27 VDD DQ30 DQ31 VSS **SDA VDD Pin Back DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ58 DQ59 VDD DQ62 DQ63 VSS **SCL VDD DQ47 97 VSS 105 107 Voltage Key CKE0 111 VDD 113 64 RAS 66 CAS DU 76 VSS 129 82 VDD 139 92 VSS DQ52 143

Pin Name ~ CS1 RAS CAS ~ 7 VDD VSS SDA SCL DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Serial data I/O Serial clock Dont use No connection

* These pins are not used in this module. These pins should NC in the system which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Pin CLK0~1 CS0~1 Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address ~ RA11, Column address ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.

Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground