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Details, datasheet, quote on part number:S3C7054
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| Part: | S3C7054 |
| Category: | Microcontrollers => 4 bit => S3C7(KS57) Series |
| Description: | Description = S3C7054 ;; ROM(KB) = - ;; RAM Nibble = - ;; I/o Pins = - ;; Interrupt (Int/Ext) = - ;; Timer/counters = - ;; Sio = - ;; LCD (Seg/Com) = - ;; ADC (BitxCh) = - ;; PWM(BitxCh) = - ;; Max. OSC.Freq. (MHz) = - ;; VDD(V) = - ;; Other Features = - ;; Package = - ;; Production Status = Eol |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download S3C7054 datasheet File size : 256 kB |
| Request For quote: | Find where to buy S3C7054
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Datasheet text preview:
S3C7044/C7048/P7048
PRODUCT OVERVIEW
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PRODUCT OVERVIEW
The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P7048 is the microcontroller which has 8K-bytes one-time-programmable ROM and the functions are same to S3C7044/C7048. With two 8-bit timer/counters, an 8-bit serial I/O interface, and eight software n-channel open-drain I/O pins, the S3C7044/C7048 offers an excellent design solution for a wide variety of general-purpose applications. Up to 36 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the S3C7044/C7048's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
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PRODUCT OVERVIEW
S3C7044/C7048/P7048
FEATURES SUMMARY
Memory · · · 512 × 4-bit RAM 4096 × 8-bit ROM: S3C7044 8192 × 8-bit ROM: S3C7048 Bit Sequential Carrier · Supports 16-bit serial data transfer in arbitrary format
Interrupts · · · 3 external interrupt vectors 4 internal interrupt vectors 2 quasi-interrupts
36 I/O Pins · · · Input only: 4 pins I/O: 24 pins N-channel open-drain I/O: 8 pins
Power-Down Modes · · Idle: Only CPU clock stops Stop: System clock stops
Memory-Mapped I/O Structure · Data memory bank 15
8-Bit Basic Timer · 4 interval timer functions
Oscillation Sources · · · Crystal or Ceramic for system clock Oscillation frequency : 0.4 6.0MHz CPU clock divider circuit (by 4. 8, or 64)
Two 8-Bit Timer/Counters · · · Programmable interval timer External event counter function Timer/counters clock outputs to TCLO0 and TCLO1 pins
Instruction Execution Times · · 0.95, 1.91, 15.3 µs at 4.19 MHz 0.67, 1.33, 10.7 µs at 6.0 MHz
Watch Timer · · Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz 4 frequency outputs to the BUZ pin
Operating Temperature · - 40 °C to 85 °C
Operating Voltage Range · · 1.8 V to 5.5 V (Main) 2.0 V to 5.5 V (OTP)
8-Bit Serial I/O Interface · · · 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable
Package Types · 42-pin SDIP, 44-pin QFP
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S3C7044/C7048/P7048
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up to 32K-byte of program memory. The arithmetic logic unit(ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operation in two cycles. CPU REGISTERS program counter A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not increment the PC is the 1-byte REF instruction which references instruction stored in a look-up table in the ROM. Whenever a reset operation or an interrupt occurs, bits PC12 though PC0 are set to the vector address. Stack pointer An 8-bit stack pointer (SP) stores addresses for stack operation. The stack area is located in general-purpose data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logic zero. During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction is executed. The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets the first register of the stack area to data memory location 0FFH. PROGRAM MEMORY In its standard configuration, the 4096 x 8-bit (S3C7404), 8192 x 8-bit (S3C7408) ROM is divided into four areas: 16-byte area for vector addresses 96-byte instruction reference area 16-byte general-purpose area (0010 001FH) 3968-byte area for general-purpose program memory (S3C7404) 8064-byte area for general-purpose program memory (S3C7408) The vector address area is used mostly during reset operation and interrupts. These 16 bytes can alternately be used as general-purpose ROM. The REF instruction references 2x1-byte or 2-byte instruction stored in reference area location 0020H 007FH. REF can also reference three-byte instruction such as JP or CALL. So that a REF instruction can reference these instruction, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused location in the REF instruction look-up area can be allocated to general-purpose use.
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