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Details, datasheet, quote on part number:S3C70F2
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| Part: | S3C70F2 |
| Category: | Microcontrollers |
| Description: | The S3c70f2/c70f4 Single-chip CMOS Microcontroller Has Been Designed For High-performance Using Samsungs Newest 4-bit Cpu Core, Sam47 ( Samsung Arrange |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download S3C70F2 datasheet File size : 278 kB |
| Request For quote: | Find where to buy S3C70F2
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Datasheet text preview:
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
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PRODUCT OVERVIEW
OVERVIEW
The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P70F4 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the same to S3C70F2/C70F4. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and its versatile 8-bit timer/counter, the S3C70F2/C70F4 offers an excellent design solution for a wide variety of general-purpose applications. Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response to internal and external events. In addition, the S3C70F2/C70F4's advanced CMOS technology provides for very low power consumption and a wide operating voltage range -- all at a very low cost.
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PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
FEATURES SUMMARY
Memory
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Bit Sequential Carrier
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512 × 4-bit data memory (RAM) 2048 × 8-bit program memory (ROM):S3C70F2 4096 × 8-bit program memory (ROM):S3C70F4
Supports 16-bit serial data transfer in arbitrary format
Interrupts
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24 I/O Pins
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Two external interrupt vectors Three internal interrupt vectors Two quasi-interrupts Data memory bank 15
I/O: 18 pins, including 8 high current pins Input only: 6 pins 4-channel mode: Internal reference (4-bit resolution) 16-step variable reference voltage 3-channel mode: External reference 150 mV resolution (worst case) Programmable interval timer Watch-dog timer
Comparator
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Memory-Mapped I/O Structure
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Two Power-Down Modes
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Idle mode: Only CPU clock stops Stop mode: System clock stops
8-bit Basic Timer
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OSCILLATION SOURCES
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Crystal, Ceramic for system clock Crystal/ceramic: 0.4 - 6.0 MHz CPU clock divider circuit (by 4. 8, or 64)
8-bit Timer/Counter 0
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Programmable interval timer External event counter function Timer/counter clock output to TCLO0 pin Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz 4 frequency outputs to BUZ pin
Instruction Execution Times
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0.95, 1.91, 15.3 µs at 4.19 MHz 0.67, 1.33, 10.7 µs at 6.0 MHz
Watch Timer
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Operating Temperature
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40 °C to 85 °C
8-bit Serial I/O Interface
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Operating Voltage Range
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8-bit transmit/receive mode 8-bit receive-only mode LSB-first or MSB-first transmission selectable Internal or external clock source
1.8 V to 5.5 V
Package Type
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30 SDIP, 32 SOP
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S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. CPU REGISTERS Program Counter A 11-bit program counter (PC) stores addresses for instruction fetch during program execution. Usually, the PC is incremented by the number of bytes of the instruction being fetched. An exception is the 1-byte instruction REF which is used to reference instructions stored in a look-up table in the ROM. Whenever a reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC1312 is reserved to support future expansion of the device's ROM size. Stack Pointer An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in the generalpurpose data memory bank 0. The SP is read or written by 8-bit instructions and SP bit 0 must always be set to logic zero. During an interrupt or a subroutine call, the PC value and the program status word (PSW) are saved to the stack area in RAM. When the service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction is executed. The stack pointer can access the stack regardless of data memory access enable flag status. Since the reset value of the stack pointer is not defined in firmware, it is recommended that the stack pointer be initialized to 00H by program code. This sets the first register of the stack area to data memory location 0FFH. PROGRAM MEMORY In its standard configuration, the 4096 × 8-bit ROM is divided into three functional areas: -- 16-byte area for vector addresses -- 96-byte instruction reference area -- 1920-byte general purpose area (S3C70F2) -- 3968-byte general purpose area (S3C70F4) The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be used as general-purpose ROM. The REF instruction references 2 × 1-byte and 2-byte instructions stored in locations 0020H007FH. The REF instruction can also reference 3-byte instructions such as JP or CALL. In order for REF to be able to reference these instructions, however, JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in the instruction reference area can be allocated to general-purpose use.
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