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Details, datasheet, quote on part number:S3C7248
 
 
Part:S3C7248
Category:Microcontrollers => 4 bit => S3C7(KS57) Series
Description:Description = ;; ROM(KB) = - ;; RAM Nibble = - ;; I/o Pins = 50 ;; Interrupt (Int/Ext) = 5/3 ;; Timer/counters = BT/WT/8T/16T ;; Sio = Yes ;; LCD (Seg/Com) = 24/4 ;; ADC (BitxCh) = 8x6 ;; PWM(BitxCh) = N/a ;; Max. OSC.Freq. (MHz) = 4.19MHz ;; VDD(V) = 2.7~6.0 ;; Other Features = - ;; Package = 80QFP ;; Production Status = Eol
Company:Samsung Semiconductor, Inc.
Datasheet:Download S3C7248 datasheet   File size : 302 kB
Request For quote:  Find where to buy S3C7248
 



Datasheet text preview:
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
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OVERVIEW
PRODUCT OVERVIEW
The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7238/C7235 offer an excellent design solution for a wide variety of applications that require LCD functions. Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to internal and external events. In addition, the S3C7238/C7235's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The S3C7238/C7235 microcontroller is also available in OTP (One Time Programmable) version, S3P7238/P7235. S3P7238/P7235 microcontroller has an on-chip 8/16-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7238/P7235 is comparable to S3C7238/C7235, both in function and in pin configuration.
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PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
FEATURES
Memory ­ ­ ­ 512 × 4-bit RAM 8 K × 8-bit ROM (S3C7238/P7238) 16 K × 8-bit ROM (S3C7235/P7235) Bit Sequential Carrier ­ Support 16-bit serial data transfer in arbitrary format
Interrupts ­ ­ ­ Three internal vectored interrupts Three external vectored interrupts Two quasi-interrupts
I/O Pins ­ ­ ­ Input only: 8 pins I/O: 24 pins Output: 8 pins sharing with segment driver outputs
Memory-Mapped I/O Structure ­ Data memory bank 15
LCD Controller/Driver ­ ­ ­ Maximum 16-digit LCD direct drive capability 32 segment, 4 common pins Display modes: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
Two Power-Down Modes ­ ­ Idle mode (only CPU clock stops) Stop mode (main or sub system oscillation stops)
8-Bit Basic Timer ­ ­ Programmable interval timer Watchdog timer
Oscillation Sources ­ ­ ­ ­ ­ Crystal, ceramic, or RC for main system clock Crystal or external oscillator for subsystem clock Main system clock frequency: 4.19 MHz (typical) Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64)
8-Bit Timer/Counter 0 ­ ­ ­ ­ Programmable 8-bit timer External event counter Arbitrary clock frequency output Serial I/O interface clock generator
Instruction Execution Times ­ ­ 0.95, 1.91, 15.3 µs at 4.19 MHz (main) 122 µs at 32.768 kHz (subsystem)
Watch Timer ­ ­ ­ Real-time and interval time measurement Four frequency outputs to BUZ pin Clock source generation for LCD
Operating Temperature ­ ­ 40 °C to 85 °C
8-Bit Serial I/O Interface ­ ­ ­ ­ 8-bit transmit/receive mode 8-bit receive only mode LSB-first or MSB-first transmission selectable Internal or external clock source
Operating Voltage Range ­ 1.8 V to 5.5 V
Package Type ­ 80-pin QFP
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S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
BLOCK DIAGRAM
W atch-Dog Timer
Basic Timer
W atch Timer
P2.3/BUZ BIAS VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 COM0-COM3 SEG0-SEG23 P8.0-P8.7/ SEG24-SEG31 P0.0/INT4 P0.1/SCK P0.2/SO P0.3/SI P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 P3.3
INT0, INT1,INT2 P1.3/TCL0 P2.0/TCLO0 8-Bit Timer/ Counter 0
RESET
XIN XTIN
XOUT XTOUT LCD Drive/ Controller
Interrupt Control Block
Clock
Instruction Register
P4.0-P4.3 P5.0-P5.3
I/O Port 3 I/O Port 4
4-Bit Accumulator Internal Interrupts I/O Port 0 Program Counter
P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7
I/O Port 6 I/O Port 7
Instruction Decoder
Program Status Word
Input Port 1
FLAGS Arithmetic and Logic Unit Stack Pointer
I/O Port 2
P8.0-P8.7/ SEG24-SEG31
I/O Port 8
I/O Port 3
512 x 4-Bit Data Memory
8/16-Kbyte Program Memory
Serial I/O Port
P0.1 P0.2 P0.3 /SCK /SO /SI
Figure 1-1. S3C7238/C7235 Simplified Block Diagram
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