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Part: LC75853NW
Category:
Interface and Interconnect
Description: 1/3 Duty LCD Display Driver With Key Input Function
Company: Sanyo Semiconductor Corporation
Datasheet: Download LC75853NW datasheet File size : 532 kB
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Datasheet text preview:
Ordering number : ENN4967C
CMOS IC
LC75853NE, 75853NW
1/3 Duty LCD Display Drivers with Key Input Function
Overview
The LC75853NE and LC75853NW are 1/3 duty LCD display drivers that can directly drive up to 126 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring.
Package Dimensions
unit: mm 3159-QFP64E
[LC75853NE]
17.2 14.0 0.35
33 48 49 32
1.0 1.6 1.0
0.8
1.6 1.0
0.15
Features
· Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) · 1/3 duty - 1/2 bias and 1/3 duty - 1/3 bias drive schemes can be controlled from serial data (up to 126 segments). · S l e e p mode and all segments off functions that are controlled from serial data · S e g m e n t output port/general-purpose output port function switching that is controlled from serial data · Serial data I/O supports CCB format communication with the system controller. · D i r e c t display of display data without the use of a decoder provides high generality. · Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. · RC oscillator circuit
· CCB is a trademark of SANYO ELECTRIC CO., LTD.
12.0 10.0
17.2 14.0 0.8
17
1.0
64 1 16
3.0max 0.8
32 17
0.1 2.7
15.6
SANYO: QFP64E
unit: mm 3190-SQFP64
[LC75853NW]
12.0 10.0 1.25
48 49
0.5
0.18
1.25
33
0.15
· CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
0.5
64
1.25
1
16
0.5
0.1 0.5
1.7max
1.25
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O3099TH (OT)/23099HA (OT)/N3095HA (OT)/52295TH (OT) No. 4967-1/24
LC75853NE, 75853NW
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 VOUT1 VOUT2 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD CE, CL, DI OSC, KI1 to KI5, TEST, VDD1, VDD2 DO OSC, S1 to S42, COM1 to COM3, KS1 to KS6, P1 to P4 S1 to S42 COM1 to COM3 KS1 to KS6 P1 to P4 Ta = 85°C Conditions Ratings 0.3 to +7.0 0.3 to +7.0 0.3 to VDD + 0.3 0.3 to +7.0 0.3 to VDD + 0.3 300 3 1 5 200 40 to +85 55 to +125 Unit V V V V V µA mA mA mA mW °C °C
Output voltage
Allowable Operating Ranges at Ta = 40 to +85°C, VSS = 0 V
Parameter Supply voltage Input voltage Symbol VDD VDD1 VDD2 VIH1 VIH2 VIL ROSC COSC fOSC tds tdh tcp tcs tch tøH tøL tr tf tdc tdr VDD VDD1 VDD2 CE, CL, DI KI1 to KI5 CE, CL, DI, KI1 to KI5 OSC OSC OSC CL, DI: Figure 2 CL, DI: Figure 2 CE, CL: Figure 2 CE, CL: Figure 2 CE, CL: Figure 2 CL: Figure 2 CL: Figure 2 CE, CL, DI: Figure 2 CE, CL, DI: Figure 2 DO, RPU = 4.7 k, CL = 10 pF*1: Figure 2 DO, RPU = 4.7 k, CL = 10 pF*1: Figure 2 19 160 160 160 160 160 160 160 160 160 1.5 1.5 0.8 VDD 0.6 VDD 0 68 820 38 76 Conditions Ratings min 4.5 2/3 VDD 1/3 VDD typ max 6.0 VDD VDD 6.0 VDD 0.2 VDD Unit V V V V V V k pF kHz ns ns ns ns ns ns ns ns ns µs µs
Input high level voltage Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time DO output delay time DO rise time
Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
Continued on next page.
No. 4967-2/24
LC75853NE, 75853NW Electrical Characteristics for the Allowable Operating Ranges
Parameter Hysteresis Power-down detection voltage Input high level current Input low level current Input floating voltage Pull-down resistance Output off leakage current Symbol VH VDET IIH IIL VIF RPD IOFFH VOH1 Output high level voltage VOH2 VOH3 VOH4 VOL1 VOL2 Output low level voltage VOL3 VOL4 VOL5 VMID1 VMID2 Output middle level voltage*2 VMID3 VMID4 VMID5 Oscillator frequency fOSC IDD1 Current drain IDD2 IDD3 CE, CL, DI: VI = 6.0 V CE, CL, DI: VI = 0 V KI1 to KI5 KI1 to KI5: VDD = 5.0 V DO: VO = 6.0 V KS1 to KS6: IO = 500 µA P1 to P4: IO = 1 mA S1 to S42: IO = 20 µA COM1 to COM3: IO = 100 µA KS1 to KS6: IO = 25 µA P1 to P4: IO = 1 mA S1 to S42: IO = 20 µA COM1 to COM3: IO = 100 µA DO: IO = 1 mA COM1 to COM3: 1/2 bias, IO = ±100 µA S1 to S42: 1/3 bias, IO = ±20 µA S1 to S42: 1/3 bias, IO = ±20 µA COM1 to COM3: 1/3 bias, IO = ±100 µA COM1 to COM3: 1/3 bias, IO = ±100 µA OSC: R = 68 k, C = 820 pF Sleep mode VDD = 6.0 V, output open, 1/2 bias, fOSC = 38 kHz VDD = 6.0 V, output open, 1/3 bias, fOSC = 38 kHz 350 300 1/2 VDD 1.0 2/3 VDD 1.0 1/3 VDD 1.0 2/3 VDD 1.0 1/3 VDD 1.0 30.4 38 0.1 VDD 1.2 VDD 1.0 VDD 1.0 VDD 1.0 0.2 0.5 1.5 1.0 1.0 1.0 0.5 1/2 VDD + 1.0 2/3 VDD + 1.0 1/3 VDD + 1.0 2/3 VDD + 1.0 1/3 VDD + 1.0 45.6 100 700 600 VDD 0.5 50 100 5.0 0.05 VDD 250 6.0 VDD 0.2 CE, CL, DI 2.7 Conditions Ratings min typ 0.1 VDD 3.0 3.3 5.0 max Unit V V µA µA V k µA V V V V V V V V V V V V V V kHz µA µA µA
Note: *2. Excluding the bias voltage generation divider resistor built into VDD1 and VDD2. (See Figure 1.)
To the common segment driver
Excluding these resistors
Figure 1
No. 4967-3/24
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