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Part: LC75874E
Category:
Interface and Interconnect
Description: 1/4-duty General-purpose LCD Display Driver
Company: Sanyo Semiconductor Corporation
Datasheet: Download LC75874E datasheet File size : 286 kB
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Datasheet text preview:
Ordering number : EN5800
CMOS LSI
LC75874E, 75874W
1/4-Duty General-Purpose LCD Display Driver
Overview
T h e LC75874E and LC75874W are 1/4-duty generalpurpose microprocessor-controlled LCD driver that can be used in applications such as frequency display in products with electronic tuning. In addition to being able to drive u p to 264 segments directly, the LC75874E and L C 7 5 8 7 4 W can also control up to 8 general-purpose output ports. Since the LC75874E and LC75874W use separate power supply systems for the LCD drive block and the logic block, the LCD driver block power-supply voltage can be set to any voltage in the range 2.7 to 6.0 V, regardless of the logic block power-supply voltage.
Package Dimensions
unit: mm 3174-QFP80E
[LC75874E]
Features
· Support for 1/4-duty 1/2-bias or 1/4-duty 1/3-bias drive t e c h n i q u e s under serial data control (up to 264 segments) · Serial data input supports CCB format communication with the system controller. · Serial data control of the power-saving mode based b a c k u p function and the all segments forced off function. · Serial data control of switching between the segment output port and general-purpose output port functions. · High generality, since display data is displayed directly without the intervention of a decoder circuit. · Independent VLCD for the LCD driver block (VLCD can b e set to any voltage in the range 2.7 to 6.0 V, regardless of the logic block power-supply voltage.) · The INH pin allows the display to be forced to the off state. · RC oscillator circuit
SANYO: QFP80E
unit: mm 3220-SQFP80
[LC75874W]
SANYO: SQFP80
· CCB is a trademark of SANYO ELECTRIC CO., LTD. · CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
31398RM (OT) No. 5800-1/16
LC75874E, 75874W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VLCD max VIN1 Input voltage VIN2 VIN3 Output voltage VOUT1 VOUT2 IOUT1 Output current IOUT2 IOUT3 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD VLCD CE, CL, DI, INH OSC VLCD1, VLCD2 OSC S1 to S66, COM1 to COM4, P1 to P8 S1 to S66 COM1 to COM4 P1 to P8 Ta = 85°C Conditions Ratings 0.3 to +7.0 0.3 to +7.0 0.3 to +7.0 0.3 to VDD + 0.3 0.3 to VLCD + 0.3 0.3 to VDD + 0.3 0.3 to VLCD + 0.3 300 3 5 200 40 to +85 55 to +125 V µA mA mW °C °C V Unit V
Allowable Operating Ranges at Ta = 40 to +85°C, VSS = 0 V
Parameter Symbol VDD VLCD VLCD1 VLCD2 VIH VIL ROSC COSC fOSC tds tdh tcp tcs tch tøH tøL tr tf tc VD D VLCD VLCD1 VLCD2 CE, CL, DI, INH CE, CL, DI, INH OSC OSC OSC CL, DI: Figure 2 CL, DI: Figure 2 CE, CL: Figure 2 CE, CL: Figure 2 CE, CL: Figure 2 CL: Figure 2 CL: Figure 2 CE, CL, DI: Figure 2 CE, CL, DI: Figure 2 INH, CE: Figure 3 10 25 160 160 160 160 160 160 160 160 160 0.8 VDD 0 43 680 50 100 Conditions Ratings min 2.7 2.7 2/3 VLCD 1/3 VLCD typ max 6.0 6.0 VLCD VLCD 6.0 0.2 VDD Unit
Supply voltage
V
Input voltage Input high-level voltage Input low-level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High-level clock pulse width Low-level clock pulse width Rise time Fall time INH switching time
V V V k pF kHz ns ns ns ns ns ns ns ns ns µs
No. 4465-No. 5800-2/16
LC75874E, 75874W Electrical Characteristics for the Allowable Operating Ranges
Parameter Hysteresis Input high-level current Input low-level current Symbol VH IIH IIL VOH1 Output high-level voltage VOH2 VOH3 VOL1 Output low-level voltage VOL2 VOL3 VMID1 VMID2 Output middle-level voltage*1 VMID3 VMID4 VMID5 Oscillator frequency fOSC IDD1 IDD2 Current drain ILCD1 ILCD2 ILCD3 CE, CL, DI, INH CE, CL, DI, INH: VI = 6.0 V CE, CL, DI, INH: VI = 0 V S1 to S66: IO = 20 µA COM1 to COM4: IO = 100 µA P1 to P8: IO = 1 mA S1 to S66: IO = 20 µA COM1 to COM4: IO = 100 µA P1 to P8: IO = 1 mA COM1 to COM4: 1/2 bias, IO = ±100 µA S1 to S66: 1/3 bias, IO = ±20 µA S1 to S66: 1/3 bias, IO = ±20 µA COM1 to COM4: 1/3 bias, IO = ±100 µA COM1 to COM4: 1/3 bias, IO = ±100 µA OSC: ROSC = 43 k, COSC = 680 pF VDD: Power-saving mode VDD: VDD = 6.0 V, outputs open, fOSC = 50 kHz VLCD: Power-saving mode VLCD: VLCD = 6.0 V, outputs open, 1/2 bias, fOSC = 50 kHz VLCD: VLCD = 6.0 V, outputs open, 1/3 bias, fOSC = 50 kHz 200 120 230 1/2 VLCD 0.9 2/3 VLCD 0.9 1/3 VLCD 0.9 2/3 VLCD 0.9 1/3 VLCD 0.9 40 50 5.0 VLCD 0.9 VLCD 0.9 VLCD 0.9 0.9 0.9 0.9 1/2 VLCD + 0.9 2/3 VLCD + 0.9 1/3 VLCD + 0.9 2/3 VLCD + 0.9 1/3 VLCD + 0.9 60 5 460 5 400 240 µA kHz V V V Conditions Ratings min typ 0.1 VDD 5.0 max Unit V µA µA
Note: *1 Excluding the bias voltage generation divider resistors built in the VLCD1 and VLCD2. (See Figure 1.)
VLCD
VLCD1
VLCD2
Figure 1
No. 4465No. 5800-3/16
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