Digchip : Database on electronics components
Electronic components database
Search:                      In section:
Member, Distributor  
Log In
Email:
Password:

Details, datasheet, quote on part number:RTC72421B
 
 
Part:RTC72421B
Description:4-bit Real Time Clock Module
Company:Seiko Instruments USA, Inc.
Datasheet:Download RTC72421B datasheet   File size : 73 kB
Request For quote:  Find where to buy RTC72421B
 



Datasheet text preview:
Real time clock module 4-bit REAL TIME CLOCK MODULE
RTC-72421/ 72423
· · · · · ·
Builtin crystal unit allows adjustment-free efficient operation. ALE input terminal available for 8048, 8051, and 8085 series. 12/24H clock switchover function and automatic leap year setting. Interrupt masking. 30 second adjustment function. Low current consumption and features a backup function.
Actual size
Specifications (characteristics) Absolute Max. rating
Symbol Item VDD Power source voltage VI/O Input and output voltage Storage temperature TSTG Condition Ta=25°C Ta=25°C RTC-72421 RTC-72423 RTC-72421 Soldering condition TSOL RTC-72423 Specifications -0.3 to 7.0 GND -0.3 to VDD+0.3 -55 to +85 -55 to +125
Under 260°C within 10 sec. (lead part) (package should be less than 150°C) Twice at under 260°C within 10 sec. or under 230°C within 3 min.
Terminal connection
Unit V °C
RTC-72421
18 17 16 15 14 13 12 11 10
1
2
3
4
5
6
7
8
9
Operating range
Item Operating voltage Operating temperature Data holding voltage CSI data holding time Operation restoring time Symbol VDD TOPR VDH tCDR tR Refer to the data holding timing RTC-72421 RTC-72423 Condition Specifications 4.5 to 5.5 -10 to 70 -40 to 85 2.0 to 5.5 2.0 min. Unit V °C V µs
RTC-72423
24 23 22 21 20 19 18 17 16 15 14 13
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
72421
STD. P CS0
ALE A0 A1 A2 A3 RD GND WR D3 D2 D1 D0 CS1 (VDD) (VDD) V DD
1 2 3 4 5 6 7 8 9 10 11 12 (VDD) and VDD are to have the same level of voltage. Do not connect it to any external terminals. NC is not connected internally.
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
72423 STD. P CS0 NC ALE A0 NC A1 NC A2 A3 RD GND WR D3 D2 D1 NC NC D0 CS1 NC (VDD) (VDD) V DD
Frequency characteristics and current consumption characteristics
Item Symbol Condition 72421 A Frequency tolerance f/fo Ta=25°C 72421 B VDD=5V 72423 A 72423 Frequency temperature characteristics Aging Shock resistance Current consumption fa S.R. IDD1 IDD2
(25°C reference temperature)
VDD=5V, Ta=25°C,
Specifications ±10 ±50 ±20 ±50 +10/-120 ±5 max. ±10 max. 10 max. 5 max.
Unit
External dimensions RTC-72421
23.1 max.
(Unit: mm)
ppm
6.8 max.
RTC72421 A EPSON 5053C
7.62 0.2 min.
-10 to +70°C
first year
ppm/Y
ppm µA
4.2
0.25 90° to 105°
CS1=0V
Exclude input/ output current
VDD=5V VDD=2V
Electrical characteristics
Item "H" input voltage "L" input voltage (1) (1) Symbol Condition VIH1 VIL1 ILK1 ILK2 VOL1 VOH VOL2 IOFFLK C1 (2) (2) VIH2 VIL2 IOL=2.5mA IOH=-400µA IOL=2.5mA V1=VDD/0V
frequency 1 MHz
Input
RTC-72423
Min. Typ. Max. 2.2 -- 0.8 ±1 --
--
Unit V µA
Applicable terminal
-- V1=VDD/0V
All inputs other than CS1
Input other than D0 to D3
16.3 max.
Input leak current (1) Input leak current (2) "L" output voltage (1) "H" output voltage "L" output voltage (2) Off leak current Input capacity "H" input voltage
0.4 2.4 -- 0.4 -- 10 20 -- 10 µA pF V V
D0 to D3
STD.P
Input other than D0 to D3
7.9
±10
RTC72423 A EPSON 6150
12.2 max. 2.5
3.3 min.
Three drops on a hard board from 75 cm or 3000G x 0.3ms x 1/2 sine wave x 3 directions
2.8 max.
65
"L" input voltage
VDD= 2 to 5.5V
4/5 VDD -- -- 1/5 VDD
CS1
0.3
D0 to D3
0.2
0.05 min.
0° to 10°
1.0
Real time clock module
Register table
Address Register
Data D3 s8 mi8 h8 D2 s4 s40 mi4 mi40 h4 D1 s2 s20 mi2 mi20 h2 h20 D0 s1 s10 mi1 mi10 h1 h10 Count Value Remarks
VIH (CS1) VIH (CS1)
Write mode (with ALE)
A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 1 0 0 1 1 0
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 S1 1 S10 0 MI 1 1 MI10 0 H1
0 to 9 0 to 5 0 to 9 0 to 5 0 to 9
0 to 2 or 0 to 1
1- second digit register 10- second digit register 1- minute digit register 10- minute digit register 1- hour digit register
PM/AM,10- hours digit register
CS1 A0 to A3 CS0
tSU
(CS1)
tSU
(A-ALE)
tH
(ALE-A)
tH
(CS1)
VIH VIL
VIH VIL
tW
VIH
(ALE)
ALE WR
VIH
VIL
0101 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0
H10
PM/AM
d4 mo4 y4 y40 w4
tSU
(ALE-W)
tW
(W)
tSU
(W-ALE)
d8 0 D1 1 D10 0 MO1 mo8 1 MO10 y8 0 Y1 1 Y10 y80 0W
d2 d1 d20 d10 mo2 mo1 mo10 y1 y2 y20 y10 w2 w1
0 to 9 0 to 3 0 to 9 0 to 1 0 to 9 0 to 6
1- day digit register 10 -day digit register 1- month digit register 10- month digit register 1- year digit register 10- year digit register Week register Control Register D
VIH VIL VIH VIH
VIL
tSU
tSU
(D-W)
tH
(R-ALE) (W-D)
D0 to D3
VIH VIL
1 1 0 1 RegD 1 1 1 0 RegE 1 1 1 1 RegF
30 sec. IRQ ADJ FLAG BUSY HOLD
Read mode (with ALE)
t1
t0
ITRPT /STND MASK STOP REST
-----
Control Register E Control Register F
CS1 A0 to A3 CS0 VIH (CS1) VIH (CS1)
TEST 24/12
0="L" level,1="H" level, REST = RESET ITRPT/ STND= INTERRUPT/ STANDARD
1) Bit does not exist. 2) Please mask AM/PM bit with 10's of hours operations. 3) Busy is read only. IRQ can only. IRQ can only be set low ("O"). 24/12 Data Bit ITRPT/STND 4) PM/AM
1 0 PM AM ITRPT STND 24 12
tSU
(CS1)
tSU
(A-ALE)
tH
(ALE-A)
VIH VIL
VIH VIL
tH (CS1)
tW
VIH
(ALE)
ALE RD
VIH
VIL
VIL
(ALE-R)
tSU
tSU (R-ALE)
VIH VIL
VOH VOL VOH VOL
5) TEST bit should be "O".
VIH
VIL
Switching characteristics (with ALE)
(Please connect ALE to VDD if the microprocessor does not have an ALE output.)
Item CS1 setup time Address setup time before ALE Address hold time after ALE ALE pulse width ALE setup time before WRITE ALE setup time before READ ALE setup time after WRITE ALE setup time after READ WRITE pulse width DATA delay time after READ DATA Hold time after READ DATA setup time before WRITE DATA hold time after WRITE CS1 hold time READ/WRITE recovery time
Symbol tSU (CS1) tSU
(A-ALE)
tPZV (R-Q)
D0 to D3
trnc (R) tPVZ (R-Q)
tH (ALE-A) tW (ALE) tSU tSU tSU
(ALE-W) (ALE-R) (W-ALE)
tSU (R-ALE) tW (W) tPZV (R-Q) tPVZ (R-Q) tSU
(D-W)
tH (W-D) tH (CS1) tREC (R/W)
Min. Max. 1000 50 50 80 0 ---0 50 50 120 ---CL=150pF 120 0 70 80 10 ---1000 200 Condition
Unit
Data holding timing
VDD 4V 2 to 4V CS1 VIH2 VIL2 Interface possible with external terminals CS1 1/5VDD Data storage mode VIL2 Interface possible with the external terminals 4V
ns
t CDR
tR
VIH2
CS0 or WR not occurred
( VDD = 5V ± 0.5V )
Block diagram
RD WR CS1 ALE CS0 A0 A1 A2 A3 D0 D1 D2 D3
OSC
DIVIDER
READ · WRITE CONTROL
ADDRESS LATCH
4
DATA BUS · BUFFER
REST STOP 30ADJ BUSY HOLD
64 HZ STD·P
4
4
CARRY PER SEC. CARRY PER MIN. CARRY PER HOUR IRQFLAG
ADDRESS DECODER
4
4
Seconds
Minutes
Hours
Days
Months
Years
Sec 1
Sec 10 Min 1 Min 10 Hou 1 Hou 10 Day 1 Day 10 Mon 1 Mon 10 Yea 1 Yea 10
Week
Reg D
Reg E
Reg F
24 /12
66