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Part: E710AHF
Category:
Discrete
Description: 500 MHZ Pin Electronics Driver, Window Comparator, And Load
Company: Semtech Corporation
Datasheet: Download E710AHF datasheet File size : 1486 kB
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Edge710 500 MHz Pin Electronics Driver, Window Comparator, and Load
EDGE HIGH-PERFORMANCE PRODUCTS Description
The Edge710 is a totally monolithic ATE pin electronics s o l u t i o n manufactured in a high-performance c o m p l e m e n t a r y bipolar process. In Automatic Test Equipment (ATE) applications, the Edge710 incorporates a driver, a load, and a window comparator suitable for very fast bidirectional channels in VLSI, Mixed-Signal, and Memory test systems. The three-statable driver is capable of generating 9V swings over a 12V range. In addition, 13V super voltage may be obtained under certain operating conditions. Separate rise and fall edge adjustments support both high speed and low speed applications, and allow for superior rise and fall time matching. An input power down mode allows extremely low leakage current in HiZ. The load supports programmable source and sink currents of ± 35 mA over a 12V range, or it can be completely d i s a b l e d . The source current, sink current, and commutating voltage are all independently set. In addition, t h e load is configurable and may be used as a programmable voltage clamp. The window comparator spans a 12V common mode range, tracks input signals with edge rates greater than 6 V/ns, and passes sub-ns pulses. An input power down mode allows for extremely low leakage measurements. The inclusion of all pin electronics building blocks into a 52 lead MQFP (10 mm body w/ internal heat spreader) offers a highly integrated solution that is traditionally implemented with multiple integrated circuits or discretes.
Features
· · · · · · · · Fully Integrated Three-Statable Driver, Window Comparator, and Dynamic Active Load 12V Driver, Load, Compare Range 13V Super Voltage Capable ± 35 mA Programmable Load Comparator Input Tracking >6V/ns Leakage (L+D+C) < 1 µA (normal mode) Leakage (L+D+C) < 25 nA (IPD mode) Small footprint (52 pin MQFP)
Functional Block Diagram
BIAS DVH
DHI DHI*
RADJ
DOUT DVR_EN DVR_EN* FADJ
DVL IPD_D QA* QA PECL IPD_C QB QB* CVB VINP CVA
VCC
Applications
· · · · VLSI Test Equipment Mixed-Signal Test Equipment Memory Testers (Bidirectional Channels) ASIC Verifiers
1K
ISC_IN VCM_IN VCM_OUT_A VCM_OUT_B LOAD BRIDGE_SC
1K
ISK_IN LD_EN LD_EN* BRIDGE_SK
VEE
Revision 2 / December 1, 2000
1
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description
Pin Name Driver DOUT DHI/DHI* DVR_EN/DVR_EN* DVH, DVL DVH_CAP DVL_CAP RADJ, FADJ BIAS IPD_D Comparator VINP CVA, CVB QA/QA* QB/QB* IPD_C PECL Load LOAD LD_EN/LD_EN* VCM_IN ISC_IN, ISK_IN 38 2, 3 44 48, 45 Load Output. Wide voltage differential inputs which activate and disable the load. High impedance analog voltage input that programs the commutating voltage. Analog current inputs which program the load source and sink currents. Should be connected to external voltage or current source through minimum 500 series resistors. Commutating buffer op amp compensation pin. Commutating voltage pins. Diode bridge connections to the output bridge that bypass the internal current sources.
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Pin #
Description
30 12, 13 14, 15 20, 19 24 25 17, 16 18 34
Driver Output. Wide voltage differential input digital pins which determine the driver high or low level. Wide voltage differential input digital pins which control the driver being active or in a high impedance state. High impedance analog voltage inputs which determine the driver high and low level. Op amp compensation pin. A 100 pF capacitor should be connected to DVH. Op amp compensation pin. A 100 pF capacitor should be connected to DVL. Input currents which determine the driver transition times. Analog current input which sets an internal bias current. TTL driver input power down control which slows the driver down and reduces the driver HiZ leakage current.
33 50, 51 6, 5 10, 11 35 7, 8
Analog voltage input to the positive input of comparators. Analog inputs which set the comparator thresholds. Differential ECL (or PECL) digital outputs of comparators A and B. TTL input power down input which slows the comparator down, but significantly reduces the VINP bias current. Unbuffered power supply level for the comparator output stages which establishes either ECL or PECL digital levels.
VCM_CAP VCM_OUT_A VCM_OUT_B BRIDGE_SC BRIDGE_SK
2000 Semtech Corp.
43 42 41 40 39
Edge710
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description (continued)
Pin Name Power Supplies, Miscellaneous CATHODE ANODE VCC VEE GND N/C 27 26 4, 31, 32, 49 1, 28, 29, 52 9, 21, 22, 36, 37, 46, 47 23 Terminals of the on-chip thermal diode string. Pin # Description
Positive power supply level. Negative power supply level. Device Ground. No connect.
VEE LD_EN LD_EN* VCC QA* QA PECL PECL GND QB QB* DHI DHI*
VCC ISC_IN GND GND ISK_IN VCM_IN VCM_CAP VCM_OUT_A VCM_OUT_B BRIDGE_SC
VEE CVB CVA
BRIDGE_SK LOAD GND GND IPD_C
52 MQFP 10 mm X 10 mm Top Side
IPD_D VINP VCC VCC DOUT VEE VEE CATHODE
2000 Semtech Corp.
RADJ BIAS DVL DVH GND GND N/C DVH_CAP DVL_CAP ANODE
3
DVR_EN DVR_EN* FADJ
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description Driver
Introduction The driver will force DOUT to one of three states: 1. DVH (Drive High) 2. DVL (Drive Low) 3. HiZ (High Impedance). Both driver digital control inputs (DHI / DHI*, DRV_EN / DRV_EN*) are "Flex Inputs" - wide voltage differential inputs capable of receiving ECL, TTL, CMOS, or custom level s i g n a l s . Single-ended operation is supported by connecting the inverting input to the appropriate DC threshold level. Drive Enable The drive enable (DRV_EN / DRV_EN*) inputs control whether the driver is forcing a voltage, or is placed in a high-impedance state. If DRV_EN is more positive than DRV_EN*, the output will force either DVH or DVL, depending on the driver data input. If DRV_EN is more negative that DRV_EN*, the output goes into a high impedance state. Do NOT leave DRV_EN / DRV_EN* floating. The established bias current follows the equation: Driver Data BIAS = (VCC - 0.7) / (Rext + 1.5). The driver data inputs (DHI / DHI*) determine whether the driver output is forcing a high or a low. If DHI is more positive than DHI*, the driver will force DVH when the driver is active. If DHI is more negative than DHI*, the driver will force DVL when active. Do NOT leave DHI / DHI* floating.
BIAS VCC
Driver Levels DVH and DVL are high input impedance voltage controlled inputs which establish the driver levels of a logical "1" and "0" respectively. Driver Level Buffer Compensation DVH_CAP and DVL_CAP are op amp compensation pins for the high and low level on-chip buffers. Each pin requires a 0.01 µF chip capacitor (with good high frequency characteristics) connected to ground. A tight layout with minimal distance between the pin and the capacitor is recommended. Driver Bias The BIAS pin is an analog current input which establishes an on-chip bias current, from which other currents are generated. This current, to some degree, also establishes the overall power consumption and performance of the chip. Ideally, an external current source would be used to minimize any part-to-part performance variation within a test system. However, a precision external resistor tied to a large positive voltage is acceptable. (See figure below.) The optimal BIAS current is a function of the RADJ and FADJ settings, and cannot be set independently.
REXT
Driver Enable DRV_EN > DRV_EN* DRV_EN > DRV_EN* DRV_EN < DRV_EN*
Driver Data DHI > DHI* DHI < DHI* X
DOUT
1.5K
DVH DVL HiZ
VEE
Table 1. Driver Control Truth Table
2000 Semtech Corp. 4
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
Driver Slew Rate Adjustment T h e driver rising and falling transition times are independently adjustable. The RADJ and FADJ pins are analog current inputs which establish the driver rise and fall times. Ideally, an external current source would be used for RADJ and FADJ. However, for most applications (where the rise and fall times are fixed), precision external resistors to a positive voltage are acceptable. The currents into RADJ and FADJ follow the equation: RADJ, FADJ = (VCC - 0.7) / (Rext + 1.5).
RADJ (FADJ)
Load
The load is capable of sourcing and sinking at least 35 mA dynamically, or being placed into a high impedance state. The load may also be configured with separate commutating voltage to act as a programmable voltage c l a m p . In addition, the load may act as a 50 transmission line termination. Load Enable The load enable input determines whether the load is active or in high impedance. If LD_EN is more positive than LD_EN*, the load is active and is capable of sourcing and sinking currents. If LD_EN is more negative than LD_EN*, the load is placed into a high impedance state. LD_EN / LD_EN* are "Flex In" - wide voltage differential inputs capable of receiving ECL, TTL, CMOS, or custom levels. Single-ended operation is supported by connecting the inverting input to the appropriate DC threshold level. Do NOT leave LD_EN / LD_EN* floating.
1.5K
Rise/Fall Adjust Current
Commutating Voltage VCM_IN is a high input impedance analog voltage input which sets the commutating voltage of the load. If LOAD is more positive than VCM_IN, the bridge will sink current from the DUT into the load. If LOAD is more negative than VCM_IN, the load will source current from the load into the DUT.
Input Power Down IPD_D is a TTL compatible input which affects both the driver speed as well as high impedance leakage. With IPD_D = 0, the driver functions normally. With IPD_D = 1, the driver is in IPD mode, where it still functions, although with slower rise and fall times, but with an extremely low HiZ leakage current. Do not leave IPD_D floating !! If IPD_D is not used, connect it to ground.
VCM_IN
DUT
VCM_IN
DUT
LOAD VCM_IN
2000 Semtech Corp. 5 www.semtech.com
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