Details, datasheet, quote on part number: SC-601R
PartSC-601R
CategoryCommunication => Telephony => Speech
DescriptionThe SC-6x Product Line Feature The Highest Quality Speech Synthesis Ics at The Lowest Data Rate in The Industry.
CompanySensory, Inc.
DatasheetDownload SC-601R datasheet
  

 

Features, Applications

Features

high-quality sound. Operates to 12.32 MHz (Performs to 12 MIPS) Single chip solution for to 24 Minutes of speech (using Mb of onboard program + data ROM) Supports high-quality synthesis algorithms Such as MX, CX, Simple CX, LX, ADPCM, and Polyphonic Music Simultaneous speech plus music capabilities Very low-power operation, ideal for handheld devices Low-voltage operation, sustainable by three batteries Reduced power stand-by modes, less than µA in deep-sleep mode

bit configurable I/O, 8 inputs with programmable pullup resistor and a dedicated interrupt (KeyScan) Direct Speaker Driver, 32 (PDM) One-bit comparator with edge-detection interrupt service Resistor-trimmed oscillator or 32.768kHz crystal reference oscillator Serial scan port for in-circuit emulation and diagnostics The SC-601 is sold in die form or 100-pin LQFP package. An emulator device is available in a ceramic package for development (SC-614-P).

Description

The is a low-cost, mixed-signal processor that combines a speech synthesizer, general-I/O, onboard ROM, and direct speaker drive in a single package. The computational unit utilizes a powerful DSP which gives the SC601 unprecedented speed and computational flexibility compared with previous devices of its type. The SC-601 supports a variety of speech and audio coding algorithms, providing range of options for speech duration and sound quality.

The device consists of a micro-DSP core, embedded program, and data memory, and a self-contained generation system. Generalpurpose periphery is comprised of 32 bits of partially configurable I/O.

The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core includes computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor, and several system and control registers. The core processor gives the SC-601 break-capability in emulation. The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is configured 32K 17-bit words. The total ROM space is divided into three areas: 1. The lower 2K words are reserved by Sensory a built-in self-test 2. The upper 30K words are for user program/data 3. An additional 1 Mb data ROM provides for to 24 minutes of speech. © 2002 Sensory Inc. P/N 80-0207-A 1

The data memory is internal static RAM. The RAM is configured 640 17-bit words. All memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency. A flexible clock generation system enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management. The periphery consists of three 8-bit wide general-purpose I/O ports and one 8-bit wide dedicated input port. The bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The input-only port has a programmable pullup option (70-k minimum resistance) and a dedicated service interrupt. These features make the input port especially useful as a key-scan interface. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the SC-601 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The functional block diagram gives an overview of the SC-601 functionality.


DESCRIPTION Port C general-purpose I/O (1 Byte) Port D general-purpose I/O (1 Byte) Port E general-purpose I/O (1 Byte) Port F general-purpose I/O (1 Byte)

Pins PD4 and PD4 may be dedicated to the comparator function, if the comparator enable bit is set.
Scan Port Control Signals SCANIN 37 SCANOUT 33 SCANCLK 36 SYNC 35 TEST 34

Scan port data input Scan port data output Scan port clock Scan port synchronization SC-601: test modes

The scan port pins must be bonded out on any SC-601 production board.

O Resistor/crystal reference out I Resistor/crystal reference in O Phase-lock-loop filter O Digital-to-analog plus output O Digital-to-analog minus output I Initialization Ground Processor power

The VSS and VDD connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required.


 

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