Details, datasheet, quote on part number: SC-604R
CategoryCommunication => Telephony => Speech
DescriptionThe SC-6x Product Line Feature The Highest Quality Speech Synthesis Ics at The Lowest Data Rate in The Industry.
CompanySensory, Inc.
DatasheetDownload SC-604R datasheet


Features, Applications


Advanced, Integrated Speech Synthesizer for High-Quality Sound Operates to 12.32 MHz (Performs to 12 MIPS) Slave Mode Enables Hours of Speech Using an External Processor and Memory Master Mode Allows 6.8 Minutes of Speech Onboard Supports High-Quality Synthesis Algorithms such as MX, CX, Simple CX, LX, ADPCM, and Polyphonic Music Simultaneous Speech Plus Music Capabilities Very Low-Power Operation, Ideal for Hand-Held Devices Low-Voltage Operation, Sustainable by Three (3) Batteries Reduced Power Standby Modes, Less Than µA in Deep-Sleep Mode 16 General-Purpose I/O Pins (in Master Mode) or 4 General-Purpose I/O Pins (in Slave Mode) Resistor-Trimmed Oscillator or 32.768-kHz Crystal Reference Oscillator Slave Interface Logic Contains 64K BytesWords Onboard ROM (2K Words Reserved) 640-Word RAM Direct Speaker Drive, 32 (PDM) One-Bit Comparator With Edge Detection Interrupt Service Serial Scan Port for In-Circuit Emulation, Monitor, and Test Available in Die Form or 64-Pin LQFP Package


The is a low-cost, mixed-signal processor that combines a speech synthesizer with a dedicated slave interface logic, generalpurpose I/O, onboard ROM, and direct speakerdrive in a single package. The computational unit uses a powerful new DSP that gives the SC604 unprecedented speed and computational flexibility compared with previous devices of its type. The SC-604 supports a variety of speech and audio coding algorithms, providing a range of options with respect to speech duration and sound quality.

The device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 16 bits of partially configurable I/O. The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block includes a computational unit (CU), data address unit, program address unit, two timers, eight-level interrupt processor, and several system and control registers. The core processor gives the SC-604break-point capability in emulation. The processor is a Harvard type for efficient DSP algorithm execution, separating program and data memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is configured 32K 17-bit words. The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Sensory, Inc. for a built-in self-test 2) The upper 30K is for user program and data space. © 2002 Sensory Inc. P/N 80-0208-B 1

The data memory is internal static RAM. The RAM is configured 640 17-bit words. All memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency. A flexible clock generation system enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536-kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management. The periphery consists of two 8-bit-wide general-purpose I/O ports when operating in master mode, or four general-purpose I/O pins in slave mode. In the master mode, the bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole output. They are controlled via addressable I/O registers. These features make the input port especially useful as a key-scan interface. Slave mode consists of four general-purpose I/O, four control pins, and eight bidirectional data pins. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its access is shared with two pins in one general-purpose I/O port. Rounding out the SC-604 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The following block diagram gives an overview of the SC-604functionality.

The is a member of the SC-6x family, which is based on the SC-614 core. For specific details about the core operations, instruction sets, register definitions, port configuration, etc., consult the SC-614 User's Guide (80-0212). The SC-604 can be used as a slave synthesizer in slave mode or can operate stand-alone in master mode. The slave mode activates logic circuitry internal to the device that gives the device a dedicated slave interface. The slave or master mode is controlled by the bit 0 of the Port (PG0). By default the device initially starts in slave mode. To change to master mode write to G port (0x2C). To change back to slave mode write 0x00 to port G bit 0 (0x2C).

In master mode, the slave logic circuitry is disabled and SC-604has 16 general-purpose I/Os. These 16 input/output pins are organized as 2-byte-wide ports (C and D), initialized as inputs. Each of the pins can be configured as a totem-pole output as a high-impedance input by setting or clearing the appropriate bit in the appropriate control register (0x14, 0x1C). When configured as an output, the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the appropriate data register (0x10, 0x18). Whether configured as input or as output, reading the data port reads the actual state of the pin. External interrupts can be caused by transitions on pins PD3, PD4, and PD5 in the master mode. These interrupts are supported whether the pins are programmed as inputs or outputs.

In slave mode, the slave logic circuitry is enabled allowing the device to have a dedicated slave interface. In this mode, only four pins of port D (PD4­PD7) are available as general-purpose I/O while the remaining pins (PD0­ PD3) are redefined as INRDY, OUTRDY, STROBE and R/W. These pins are used to operate the slave interface. The SC-604controls the INRDY and OUTRDY pins to let the external microcontroller know when the slave is ready to accept or transmit data. The external microcontroller controls the R/W and STROBE pins of SC-604to sequence the read/write data flow. Each read or write sequence generates an interrupt that needs to be serviced by an interrupt service routine. These interrupt service routines need to be written by the code developer. The INT3 interrupt service routine indicates that the host has completed the write sequence, and the slave should read the data from port A. The INT4 interrupt service routine indicates the host has completed the read sequence. An interrupt is not generated when a read/write is done on port G bit 0 (PG0). The slave interface consists of: 8-bit bidirectional data bus (PC0­PC7) 2 status outputs: INRDY/PD0, and OUTRDY/PD1 2 control inputs: STROBE/PD2, and R/W/PD3 4 general-purpose I/Os (PD4­PD7) Port C is used an 8-bit bidirectional data bus. When data to be sent to the host, it needs to be written to port C data register (0x10). When data is read from the host, it needs to be read from port A data register (0x00). Port A pins are not physically brought outside the device but are internally connected with the pins of port C.

Initialize the host processor first. The host must hold the slave RESET pin low until the slave STROBE pin can be held high by the host throughout the slave initialization process. The INRDY and OUTRDY pins are set high by the slave on the rising edge of the slave RESET pin.

Write 0x00 to port A (0x00), port C (0x10), port D (0x18) data registers. Configure the port C (PC0­PC7), port D0, and port D1 as output ports. (Write 0xFF to port C (0x14) and 0x03 to port D (0x1C) control registers) © 2002 Sensory Inc. P/N 80-0208-B 3


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