|Company||Silicon Storage Technology, Inc.|
|Datasheet||Download SST89V564-25-I-TQJ datasheet
8-bit 8051 Family Compatible Microcontroller (MCU) with Embedded SuperFlash Memory is 5V Operation to 40 MHz Operation is 3V Operation to 25 MHz Operation at 3V Fully Software and Development Toolset Compatible as well as Pin-For-Pin Package Compatible with Standard 8xC5x Microcontrollers 1 KByte Register/Data RAM Dual Block SuperFlash EEPROM SST89E564/SST89V564: 64 KByte primary block + 8 KByte secondary block (128-Byte sector size) SST89E554/SST89V554: 32 KByte primary block + 8 KByte secondary block (128-Byte sector size) Individual Block Security Lock Concurrent Operation during In-Application Programming (IAP) Block Address Re-mapping Support External Address Range to 64 KByte of Program and Data Memory Three High-Current Drive Pins (16 mA each) Three 16-bit Timers/Counters Full-Duplex Enhanced UART Framing error detection Automatic address recognition Eight Interrupt Sources at 4 Priority Levels Watchdog Timer (WDT) Four 8-bit I/O Ports (32 I/O Pins) Second DPTR register Reduce EMI Mode (Inhibit ALE through AUXR SFR) SPI Serial Interface TTL- and CMOS-Compatible Logic Levels Brown-out Detection Extended Power-Saving Modes Idle Mode Power Down Mode with External Interrupt Wake-up Standby (Stop Clock) Mode PDIP-40, PLCC-44 and TQFP-44 Packages Temperature Ranges: Commercial +70°C) Industrial to +85°C)
SST89V564, SST89E554, and SST89V554 are members of the FlashFlex51 family of 8-bit microcontrollers. The is a family of microcontroller products designed and manufactured on the state-of-the-art SuperFlash CMOS semiconductor process technology. The device uses the same powerful instruction set and is pin-forpin compatible with standard 8xC5x microcontroller devices. The device comes with 72/40 KByte of on-chip flash EEPROM program memory using SST's patented and proprietary CMOS SuperFlash EEPROM technology with the SST's field-enhancing, tunneling injector, split-gate memory cells. The SuperFlash memory is partitioned into 2 independent program memory blocks. The primary SuperFlash Block 0 occupies 64/32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 8 KByte of internal program memory space. The 8-KByte secondary SuperFlash block can be mapped to the lowest location of the 64/32 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory. The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST's device. During the power-on reset, the
device can be configured as a slave to an external host for source code storage as a master to an external host for In-Application Programming (IAP) operation. The device is designed to be programmed "In-System" and "In-Application" on the printed circuit board for maximum flexibility. The device is pre-programmed with an example of bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the "IAP" operation. An example of bootstrap loader is for the user's reference and convenience only. SST does not guarantee the functionality or the usefulness of the sample bootstrap loader. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code. In addition to 72/40 KByte of SuperFlash EEPROM program memory on-chip, the device can address to 64 KByte of external program memory. In addition x 8 bits of on-chip RAM, to 64 KByte of external RAM can be addressed. SST's highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs. These advantages translate into significant cost and reliability benefits for our customers.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. FlashFlex, In-Application Programming, IAP, and SoftLock are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
PRODUCT DESCRIPTION. 1 LIST OF FIGURES. 4 LIST OF TABLES. 5 1.0 FUNCTIONAL BLOCKS. 6 Functional Block Diagram. 6 2.0 PIN ASSIGNMENTS. 7 2.1 Pin Descriptions. 8 3.0 MEMORY ORGANIZATION. 10 3.1 Program Memory. 10 3.2 Program Memory Block Switching. 11 3.2.1 Reset Configuration of Program Memory Block Switching. 12 3.3 Data Memory. 12 3.4 Dual Data Pointers. 12 3.5 Special Function Registers (SFR). 12 4.0 FLASH MEMORY PROGRAMMING. 24 4.1 External Host Programming Mode. 24 4.1.1 Product Identification. 4.1.2 Arming Command. 4.1.3 Detail Explanation of the External Host Mode Commands. 4.1.4 External Host Mode Clock Source. 4.1.5 Flash Operation Status Detection Via External Host Handshake. 4.1.6 Step-by-step instructions to perform External Host Mode commands. 4.1.7 Flash Memory Programming Timing Diagrams with External Host Mode. In-Application Programming Mode Clock Source. Memory Bank Selection for In-Application Programming Mode. IAP Enable Bit. In-Application Programming Mode Commands. Polling. Interrupt Termination.
5.0 TIMERS/COUNTERS. 36 6.0 SERIAL I/O. 36 6.1 Enhanced Universal Aysnchronous Receiver/Transmitter (UART). 36 6.1.1 Framing Error Detection. 36 6.1.2 Automatic Address Recognition. 36 6.2 Serial Peripheral Interface (SPI). 37
Preliminary Specifications 7.0 WATCHDOG TIMER. 39 8.0 SECURITY LOCK. 40 8.1 Hard Lock. 40 8.2 SoftLock. 40 8.3 Security Lock Status. 40 9.0 RESET. 43 9.1 Power-On Reset. 43 9.2 Software Reset. 43 9.3 Brown-out Detection Reset. 43 9.4 Interrupt Priority and Polling Sequence. 43 9.5 Power-Saving Modes. 44 9.5.1 Idle Mode. 44 9.5.2 Power Down Mode. 44 9.5.3 Standby Mode (Stop Clock). 44 9.6 Clock Input Options. 46 9.7 Recommended Capacitor Values for Crystal Oscillator. 46 10.0 ELECTRICAL SPECIFICATION. 47 Absolute Maximum Stress Ratings. 47 10.1 Operation Range. 47 10.2 Reliability Characteristics. 10.3 DC Electrical Characteristics. 10.4 AC Electrical Characteristics. 10.5 AC Characteristics. 52 11.0 PRODUCT ORDERING INFORMATION. 56 11.1 Valid Combinations. 56 12.0 PACKAGING DIAGRAMS. 57
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