|Category||DSPs (Digital Signal Processors)|
|Description||High Performance, Low-power, Synthesizable DSP Core
The ZSP540 processor core is a high-performance/power-efficient Quad-MAC/Six-ALU implementation of the ZSP G2 architecture. The ZSP540 utilizes a 16-bit architecture with extensive 32-bit capabilities and sets an unmatched balance of performance, power and memory utilization efficiency. The Z.Turbo accelerator provides the SOC designer with the option to extend the ZSP540 Instruction Set and the ability to add application-specific acceleration logic.LSI Logic ZSP processor cores are fully synthesizable and completely technology independent. The cores have been proven in ASICs and standard products alike. The ZSP architectures have been optimized for optimal code density, energy efficiency, compiler performance and system integration.
1. 4+1 instructions per cycle, Quad-MAC/Six-ALU DSP core
Customizable instruction set using Z.turbo port
Extensive 32-bit and 40-bit support w/ 24-bit address space
Easy to program Orthogonal, 16/32-bit load-store instruction set
Hardware controlled pipeline protection
Embedded trace and profiling capability
Synthesizable, static, single phase clocked design w/ optional AMBA/AHB support
Code compatible with all other ZSP cores
|Company||Silicon Storage Technology, Inc.|
|Datasheet||Download ZSP540 datasheet
The ZSP540 processor core is a high-performance/power-efficient QuadMAC/Six-ALU implementation of the ZSP® G2 architecture. The ZSP540 utilizes a 16-bit architecture with extensive 32-bit capabilities and sets an unmatched balance of performance/power/size and memory utilization efficiency. The Z.Turbo feature provides the SOC designer with the option to extend the ZSP540 Instruction Set and the ability to add application-specific acceleration logic.
Quad-MAC/Six-ALU DSP core 4+1 instructions per cycle 350MHz, 8-stage pipeline design to 1750 million instructions/sec Dual 64-bit wide Load/Store data ports Z.Turbo coprocessor extensions capable
2.5/3G wireless baseband processing Multimedia wireless and mobile devices Cable/xDSL Wireless LAN (WLAN) Set-top box and home gateways Multi-channel Voice Over IP (VoIP) Software Defined Radio (SDR)
24-bit address space HW managed instructions scheduling HW/SW controlled power management Real-time trace and profiling capability Full AMBA/AHB support (optional) JTAG debug interface Static, single phase clocked design Compatible with all other ZSP cores
High-performance DSP capabilities Excellent power/cost/speed balance Excellent multimedia audio/video processing Power efficient baseband processing performance DSP and system control functions handling capabilities
Embedded control processing efficiency 32-bit addressing capabilities 16 and 32-bit standard instruction set Extensive 32-bit and 40-bit support Easy to program instruction setPipeline Control Unit (PCU) Interrupt Control
Load/store register based instructions Outstanding code density User extensible instruction set
Highly optimized C-compiler Multimedia, voice and wireless experts Local support by ZSP solution experts
Timers Multiply/ALU Unit 0 40-bit ALU 16x16 MAC 16x16 MAC Multiply/ALU Unit 1 40-bit ALU 16x16 MAC 16x16 MAC ALU Unit 16-bit ALU 16-bit ALU
LSI Logic ZSP cores are licensable and available as a fully synthesizable and technology independent. The ZSP Cores have been proven in ASICs and are also available as standard general-purpose DSP and Application Specific Standard Products (ASSP) from LSI Logic and licensees of the ZSP cores. The ZSP540 is power-efficient/high-performance Quad-MAC DSP core implementation of the ZSP G2 architecture version and is software compatible with all other ZSP cores enabling code reuse and effortless design migration and scalability. The ZSP540 features instruction grouping, instruction parallelism and pipeline control all done by hardware making it seamless and easy to program. Highly optimized C-Compilers are available minimizing the need for assembly level programming.
For more information please call: LSI Logic Corporation Headquarters 1621 Barber Lane Milpitas, CA 95035 Tel: 866.574.5741 (within U.S. and Canada) 1.408.954.3108 (outside U.S. and Canada) Technical Support: 800.633.4545 Corporate Website www.lsilogic.com Sales Office Locations www.lsilogic.com/contacts Additional information on the ZSP540 is available at: http://www.zsp.com/zsp540.html
ZSP cores are available as a synthesizable, fully static/single-phased design AMBA/AHB (optional) or native ZSP bus interfaces are available Co-verification and System modeling support available by various providers
Highly optimized development kits are available from LSI Logic and Green Hills Multi-core ARM/ZSP support is available through Green Hill and ARM's RealView JTAG probes for single/multi-core support available from various providers Embedded real-time trace and application profiling supported ZOpenTM software development framework enables rapid integration and
LSI Logic logo design, ZOpen and ZSP are trademarks or registered trademarks of LSI LogicCorporation. AMBA is a registered trademark ofARM Ltd. All other brand and product names maybe trademarks of their respective companies. LSI Logic Corporation reserves the right to makechanges to any products and services herein at anytime without notice. LSI Logic does not assume anyresponsibility or liability arising out of theapplication or use of any product or servicedescribed herein, except as expressly agreed to inwriting by LSI Logic; nor does the purchase, lease,or use of a product or service from LSI Logicconvey a license under any patent rights,copyrights, trademark rights, or any other of theintellectual property rights of LSI Logic or of thirdparties. Copyright ©2004 by LSI Logic Corporation. All rights reserved.reuse of software modules developed by different 3rd parties
Architecture evaluation boards Standalone FPGA prototyping boards ARM Integrator core modules available Multi-media audio/video development platform Audio development platform
|Some Part number from the same manufacture Silicon Storage Technology, Inc.|
|SST89E52RD 89 Series - FlashFlex51 MCUThe SST89E5xRD2/RD and SST89V5xRD2/RD are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SST's patented and proprietary|
SST29EE020-250-4I-EH : 2 Mbit (256K X 8) Page-mode EePROM
SST39LF200A : 2 Mbit / 4 Mbit / 8 Mbit ( X16 ) Multi-purpose Flash
SST39VF800A-90-4C-B3K : Multi-Purpose Flash (MPF) Voltage = 3 to 3.6 ;; Density = 2Mb ;; Organization = 128Kb X 16 ;; Speed = 45 NS ;; Temp. = Commercial ;; Package = Tfbga/tbga
SST58SM008 : Ata-disk Module
SST89C554-33-I-NI : Flashflex 51 MCU
SSY39L200554CE2 : 2 MBIT / 4 MBIT / 8 MBIT ( X 16 ) Multi - Purpose Flash
SST34HF1622D-70-4E-LPE : 32 Mbit Concurrent Superflash + 16 Mbit Psram Combomemory
SST89V54RD2-33-C-QIE1 : Flashflex51 MCU
SST89E54RD2-40-I-QIF2 : Flashflex51 MCU
SST29LE010A-90-4I-NH : 1 Megabit (128k x 8) Page Mode Eeprom
ADSP-21160M : Sharc, 80 Mhz, 600 Mflops, 3.3v I/O, 2.5v Core, Floating Point. SUMMARY High-Performance 32-Bit DSP--Applications in Audio, Medical, Military, Graphics, Imaging, and Communication Super Harvard Architecture--Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive, Zero-Overhead I/O Backwards-Compatible--Assembly Source Level Compatible with Code for ADSP-2106x DSPs Single-Instruction-Multiple-Data.
ADSP-2184 : DSP Block. 16-bit, 40 Mips, 5v, 2 Serial Ports, Host Port, 20KB RAM. PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 Cycle Recovery from Power-Down Condition Low Power.
HMU17 : DSP Block. 16x16-bit CMOS Parallel Multipliers. The HMU16 and HMU17 are high speed, low power CMOS x 16-bit multipliers ideal for fast, real time digital signal processing applications. The X and Y operands along with their mode controls (TCX and TCY) have 17-bit input registers. The mode controls independently specify the operands as either two's complement or unsigned magnitude format, thereby.
HMU17/883 : DSP Block. 16 X 16-Bit CMOS Parallel Multiplier. DUCT CT E PRO RODU UTE P ter en E SUB SSIBL ical Suppor.com/tsc ch rsil FOR our Te or www.inte S 1-888-I This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph x 16-Bit Parallel Multiplier with Full 32-Bit Product High-Speed (45ns) Clocked Multiply Time Low Power CMOS Operation - ICCSB = 500µA.
LMU08 : DSP Block. 8 X 8-bit Parallel Multiplier. The LMU08 and LMU8U are highspeed, low power 8-bit parallel multipliers. They are pin-for-pin equivalents with TRW TMC208K and TMC28KU type multipliers. Full military ambient temperature range operation is attained by the use of advanced CMOS technology. This facilitates use of the LMU08 product as a double precision operand in 8-bit systems. The LMU8U.
MB86330 : DSP Block. CMOS 16-bit Fixed-point DSP. The a 16-bit fixed-point DSP (Digital Signal Processor) that is based on Fujitsu-specific Dual-MAC architecture, and can implement product addition operations and double transfer at a high rate and under low power consumption. The DSP supports a set of instructions optimum for digital signal processing in communications applications such as handy phones.
SMJ320C31 : TMS320 Family. Processed to MIL-PRF-38535 (QML) Operating Temperature Ranges: Military (M) 125°C Special (S) to 105°C SMD Approval High-Performance Floating-Point Digital Signal Processor (DSP): V) 33-ns Instruction Cycle Time 330 Million Operations Per Second (MOPS), 60 Million Floating-Point Operations Per Second (MFLOPS), 30 Million Instructions Per Second.
TDA1301T : TDA1301T; Digital Servo Processor (DSIC2). The DSIC2 realizes the following servo functions: Diode signal preprocessing Focus servo loop Radial servo loop Sledge motor servo loop Three-line serial interface via the microcontroller The other include: Full digital signal processing Low power consumption, down to 30 mW Low voltage supply 5.5 V Integrated analog-to-digital converters and digital.
TMS320C30 : TMS320 Family. Digital Signal Processor. High-Performance Floating-Point Digital Signal Processor (DSP) V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS V) 60-ns Instruction Cycle Time 183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS V) 74-ns Instruction Cycle Time 148.5 MOPS, 27 MFLOPS, 13.5 MIPS 32-Bit High-Performance CPU / 32-Bit.
TMS320C541-40 : TMS320 Family. Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators × 17-Bit Parallel Multiplier Coupled a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare.
TMS320C54CSTGGU : TMS320 Family. ti TMS320C54CST, Digital Signal Processor (DSP Only) For Client-side Telephony.
TMS320DM640 : Video/imaging Fixed-point Digital Signal Processorthe TMS320C64x TMS320DM640 Devices) Are The Highest-performance Fixed-point DSP Generation in The TMS320C6000 DSP Platform. The TMS320DM641 And TMS320DM640 (DM641 And DM640) Devices Are Based on The Second-generation High-performance, Advanced Velociti Very-long-instruction-word (VLIW) Architecture (VelociTI.2.
TMS320LC31 : 320 Family. Digital Signal Processors. High-Performance Floating-Point Digital Signal Processor (DSP): V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS V) 33-ns Instruction Cycle Time 330 MOPS, 60 MFLOPS, 30 MIPS V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS,.
TMS320LC541B-50 : TMS320 Family. Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators × 17-Bit Parallel Multiplier Coupled a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare.
dsPIC30F6015 : dsPIC30F Motor Control 16-bit Digital Signal Controller. Seamless migration options from this device to dsPIC33F and PIC24 devices in similar packages. High-Performance Modified RISC CPU: # Modified Harvard architecture # C compiler optimized instruction set architecture # 84 base instructions with flexible addressing modes # 24-bit wide instructions,.
TMS320C5514 : Fixed-Point Digital Signal Processor The TMS320C5514 is a member of TI\'s TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The TMS320C5514 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power.
MSC8251 : Single-Core Digital Signal Processor •One StarCore SC3850 DSP subsystems, with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug.
MSC8254 : Quad-Core Digital Signal Processor • Four StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers,.