Single Gate and Drain Biases 25 dBm Typical P1 dB Output Power at 31 GHz 11 dB Typical Small Signal Gain 0.25 µm Ti/Pd/Au Gates 100% On-Wafer RF and DC Testing 100% Visual Inspection MT 2010
Skyworks' two-stage reactively-matched Ka band GaAs MMIC power amplifier has a typical of 25 dBm with 10 dB associated gain and 15% power added efficiency at 31 GHz. The chip uses Skyworks' proven 0.25 µm MESFET technology, and is based upon MBE layers and electron beam lithography for the highest uniformity and repeatability. The FETs employ surface passivation to ensure a rugged, reliable part with through-substrate via holes and gold-based backside metallization to facilitate solder or epoxy die attach processes. Single gate and drain bias pads cover both stages, with the added convenience that the chip can be wire bonded from either side for either bias. All chips are screened for gain, output power, efficiency and S-parameters prior to shipment for guaranteed performance. A broad range of applications exist in both the military and commercial areas where high power and gain are required.
Dimensions indicated in mm. All DC (V) pads are 0.1 mm and RF In, Out pads are 0.07 mm wide. Chip thickness = 0.1 mm.
Characteristic Operating Temperature (TC) Storage Temperature (TST) Bias Voltage (VD) Power In (PIN) Junction Temperature (TJ) Value +150°C 7 VDC 22 dBm 175°C
Parameter Drain Current (at Saturation) Small Signal Gain Input Return Loss Output Return Loss Output Power 1 dB Gain Compression Saturated Output Power Gain at Saturation Two-Tone Output Third-Order Thermal Resistance2
1. Not measured a 100% basis. 2. Calculated value based on measurement of discrete FET.
3. Typical represents the median parameter value across the specified frequency range for the median chip.
Skyworks Solutions, Inc.  241-7000· Fax  241-7906· Email email@example.com· www.skyworksinc.com
Typical Small Signal Performance S-Parameters (VDS 6 V)
Output Power and Relative Third-Order Intermodulation Products = 31 GHz, VDS 6 V, VGS -1 V
The AA032P1-00 can be biased from either or both sides for both gate and drain biases. For biasing on, adjust VGS from zero to approximately -1 V. Adjust VDS from zero to the desired value V6 V recommended). Adjust VGS to achieve the desired IDS (400 mA recommended). For biasing off, reverse the biasing on procedure.