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Part: CXA1866Q
Category:
Description: 6-bit 140MSPS Flash A/D Converter
Company: Sony Electronics
Datasheet: Download CXA1866Q datasheet File size : 399 kB
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CXA1866Q
6-bit 140MSPS Flash A/D Converter For the availability of this product, please contact the sales office.
Description The CXA1866Q is a 6-bit ultra-high-speed flash A/D converter IC capable of digitizing analog signals at the maximum rate of 140MSPS. The digital input level is compatible with ECL 100K/10KH/10K. Features · Ultra-high-speed operation with maximum conversion rate of 140MSPS · Low input capacitance: 7pF · Wide analog input bandwidth: 210MHz · Low power consumption: 325mW · Low error rate · Excellent temperature characteristics · 1 : 2 demultiplexed output (TTL level)
VRBS
48 pin QFP (Plastic)
Structure Bipolar silicon monolithic IC Applications · Magnetic recording (PRML) · Communications (QPSK, QAM) · Liquid crystal display
VRTS
22
15
19
VRB 16
VIN
Block Diagram
Reference Resistance Chain
21
VRT
COMPARATOR
6bit Latch 41 DVEE 6 INV 27 CLatchA CD NCCLK 25 46 DGND1 23 AVEE
CCLK 26
20 AGND
45 DGND2 42 DGND3 CLatchB 6 DCLK 11 CD NDCLK 12 TTLOUT 47 6 48 DVCC2 DVCC1
7
6
5
4
3
2
35 34 33 32 31 30
CD; Clock Driver
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
P2D5 (MSB)
1
P1D5 (MSB)
P2D0 (LSB)
P1D0 (LSB)
P2D4
P2D3
P2D2
P2D1
P1D4
P1D3
P1D2
P1D1
E93Z35B77
CXA1866Q
Absolute Maximum Ratings (Ta = 25°C) · Supply voltage AVEE, DVEE DVCC1 · Analog input voltage VIN · Reference input voltage VRT, VRB I VRT VRB I · Digital input voltage DIN2 I CCLK NCCLK I, I DCLK NDCLK I · Digital output current ID0 to ID6 · Storage temperature Tstg · Ambient operating temperature Ta · Allowable power dissipation PD Recommended Operating Conditions · Supply voltage AVEE, DVEE AVEE DVEE AGND DGND3 DVCC1 · Reference input voltage · Analog input voltage · Digital input voltage · · · · · · CCLK, NCCLK frequency DCLK, NDCLK frequency CCLK, NCCLK duty DCLK, NDCLK duty CCLK-DCLK time difference4 Operating temperature VRT VRB VIN DIN (H) DIN (L) Fcclk Fdclk Dcclk Ddclk tdcd Ta Min. 5.5 0.05 0.05 4.75 0.1 2.2 VRB 1.1
7.0 to +0.5 0.5 to +7.0 2.7 to +0.5 2.7 to +0.5 2.5 4.0 to +0.5 2.5 30 to +30 65 to +150 20 to +75 750 Typ. 5.2 0 0 5.0 0 2.0 Max. 4.75 0.05 0.05 5.25 0.1 0.8 VRT 1.5 140 70 60 60 TPWH + 1 +75
V V V V V V V mA °C °C mW
V V V V V V V V MHz MHz % % ns °C
40 40 TPWL + 2 20
50 50 0
1 DVCC = DVCC1, DVCC2 2 DIN = CCLK, NCCLK, DCLK, NDCLK, INV
P1D5 (MSB)
3 DGND = DGND1, DGND2, DGND3 4 Refer to the Timing Chart 1 for TPWL, TPWH.
P1D0 (LSB)
DGND3
DGND3
DVCC2
P1D4
P1D3
36 35 34 33 32 31 30 29 28 27 26 25
DVCC2 37 DVCC1 38 DGND1 39 DGND2 40 DVEE 41 DGND3 42 DVCC2 43 DVEE 44 DGND2 45 DGND1 46 DVCC1 47 DVCC2 48 CXA1866Q (Top View)
INV
CCLK
P1D2
P1D1
NCCLK
Pin Configuration. Pins without names are NC pins (not connected).
24 23 22 21 20 19 18 17 16 15 14 13 AGND VRB VRBS AVEE AVEE VRTS VRT AGND VIN
1
2
3
4
5
6
7
8
9 10 11 12
P2D5 (MSB)
DGND3
P2D0 (LSB)
2
DGND3
NDCLK
P2D4
DVCC2
DCLK
P2D1
P2D2
P2D3
CXA1866Q
Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol I/O
Standard voltage level
VRT
Equivalent circuit
Description Top reference voltage input (= 0V). This is the top reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the plus side of the input analog signal amplitude. VRT sense output. This is the voltage sense pin for VRT. Bottom reference voltage input (= 2V). This is the bottom reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the minus side of the input analog signal amplitude. VRB sense output. This is the voltage sense pin for VRB.
AGND
21
VRT
I
0V
VRTS
Comparator 1
22
VRTS
O
0V
Comparator 2
Comparator 31
Comparator 32
16
VRB
I
2V
Comparator 63 VRBS
15
VRBS
O
2V
VRB
19
VIN
I
VRTS to VRBS
VIN
Analog input. The input range is 2Vp-p.
AVEE
26
CCLK
I
ECL
CCLK clock input. This is the conversion clock, and is an ECL level input. CCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (1.3V). Only CCLK input can be used for operation with the NCCLK input left open,but complementary input is recommended to attain fast and stable operation. DCLK clock input. This is the 1:2 DMPX latch clock; input a clock of 1/2 frequency of CCLK. Data are output from DMPX port 1 and port 2 synchronously with the rising edge of this signal. This is an ECL level input. DCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (1.3V). Only DCLK input can be used for operation with the NDCLK input left open, but complementary input is recommended to attain fast and stable operation. 3
DGND1
25
NCCLK
I
ECL
r CCLK (DCLK) NCCLK (NDCLK) r 500 r r
500
11
DCLK
I
ECL
r DVEE
r 1.3V
12
NDCLK
I
ECL
CXA1866Q
Pin No.
Symbol
I/O
Standard voltage level
DGND1
Equivalent circuit
Description
r r 1.3V
27
INV
I
ECL
INV
500
r
r DVEE
1.3V
Digital output polarity inversion input. This is an ECL level input. This input inverts the polarity of the digital outputs P1D0 to P1D5, and P2D0 to P2D5. (Refer to the Output Code Table.) When left open, this signal is maintained at the low level.
30 31 32 33 34 35 2 3 4 5 6 7
P1D0 P1D1 P1D2 P1D3 P1D4 P1D5 P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 -- -- -- -- -- +5.0V +5.0V 0V 0V 0V +5V power supply for TTL level internal circuit. +5V power supply for TTL level output buffers (P1D0 to P2D5). Ground for DVEE digital circuit. Ground for DVcc1 digital circuit. Ground for DVcc2 digital circuit. Ground for AVEE analog circuit . Used as the ground for the comparator input buffers, latches, etc. Separated from DGND. 5.2V power supply for digital circuit. Connected internally with AVEE. (Resistance is 4 to 6.) 5.2V power supply for analog circuit. Connected internally with DVEE. (Resistance is 4 to 6.)
DGND2 DGND3 DVCC1 DVCC2
These pins are for the 6 bits of digital output data for DMPX port 1. P2D5 is the MSB, and P2D0 is the LSB. These are TTL level outputs.
O
TTL
100K
P1D0 to D5 P2D0 to D5
These pins are for the 6 bits of digital output data for DMPX port 2. P2D5 is the MSB, and P2D0 is the LSB. These are TTL level outputs.
38, 47 DVCC1
9, 28, 37, DVCC2 43, 48
39, 46 DGND1
40, 45 DGND2
1, 8, 29, DGND3 36, 42
17, 20 AGND
--
0V
41, 44 DVEE
--
5.2V
14, 23 AVEE
--
5.2V
4
CXA1866Q
Electrical Characteristics Item Resolution DC characteristics Integral linearity error Differential linearity error No missing code Analog input Analog input capacitance Analog input resistance Input bias current Reference input Reference resistance Reference resistance current Offset voltage VRT VRB Digital input Logic high level Logic low level Logic high current Logic low current Input capacitance Switching characteristics Maximum conversion frequency Aperture jitter Sampling delay Digital output Logic high level Logic low level Output delay Output rising time Output falling time Dynamic characteristics Analog amplitude input bandwidth S/N ratio Symbol n EIL EDL
(Ta = 25°C, AVEE = DVEE = 5.2V, DVCC = 5V, VRT = 0V, VRB = 2V) Conditions Min. Typ. 6 Fc = 140MHz Fc = 140MHz Guaranteed CIN RIN IIN RREF Iref EOT EOB VIH VIL IIH IIL 1.13 VIH = 0.8V VIL = 1.6V 0 50 3.5 FC Taj Tds VOH VOL tdo tr tf Finb IOUT = 2mA IOUT = 1mA ZL = 25pF ZL = 25pF, 0.5V to 2.4V ZL = 25pF, 0.5V to 2.4V 2.7 2.0 1.2 1.2 210 36 34 32 109 20 40 325 32 0.5 8.0 Error rate1E-9 TPS1 140 5.0 1.0 1.50 50 50 VIN = 1V + 0.07Vrms, DC VIN 70MHz 2V VIN 0V 2V VIN 0V 7 200 110 225 9 25 25 pF k µA mA mV mV V V µA µA pF MSPS ps ns V V ns ns ns MHz dB dB dB TPS1 mA mA mW ±0.2 ±0.2 Max. Unit bits LSB LSB
Error rate Power supply Supply current Power consumption 1 TPS: Times Per Sample
VIN = 2Vp-p, p-p value = 3dB down input frequency SNR1 Fc = 140MHz, Fin = 1MHz SNR2 Fc = 140MHz, Fin = 35MHz SNR3 Fc = 140MHz, Fin = 70MHz Fc = 140MHz, error > 4LSB ICC IEE Pd DVCC = +5V AVEE = DVEE = 5.2V
60
5
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